Inventor
RAO VASANT B
US10 patents
Patents
10 patentsUS6763504B2Jul 13, 2004
Method for reducing RC parasitics in interconnect networks of an integrated circuit
IBM20 citations87
US9836572B2Dec 5, 2017
Incremental common path pessimism analysis
IBM2 citations72
US9613171B1Apr 4, 2017
Multi-cycle signal identification for static timing analysis
IBM2 citations72
US9501608B1Nov 22, 2016
Timing analysis of circuits using sub-circuit timing models
IBM4 citations71
US9785737B2Oct 10, 2017
Parallel multi-threaded common path pessimism removal in multiple paths
IBM1 citations52
US10360329B2Jul 23, 2019
Multi-cycle signal identification for static timing analysis
IBM0 citations51
US10325059B2Jun 18, 2019
Incremental common path pessimism analysis
IBM0 citations51
US9760664B2Sep 12, 2017
Validating variation of timing constraint measurements
IBM0 citations45
US9760665B2Sep 12, 2017
Validating variation of timing constraint measurements
IBM0 citations45
US7643981B2Jan 5, 2010
Pulse waveform timing in EinsTLT templates
IBM0 citations35