Inventor

SITARAM ARKALGUD R

US62 patents

⚠️ This page may combine multiple inventors who share the name “SITARAM ARKALGUD R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SITARAM ARKALGUD R

INVENSAS CORP

Integrated circuits protected by substrates with cavities, and methods of manufacture

Structures and methods for reliable packages

Structures and methods for reliable packages

Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies

Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture

Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates

Thermal vias disposed in a substrate proximate to a well thereof

Thermal vias disposed in a substrate proximate to a well thereof

Structure and method for integrated circuits packaging with increased density

Capacitive coupling in a direct-bonded interface for microelectronic devices

Integrated circuits protected by substrates with cavities, and methods of manufacture

Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies

Localized sealing of interconnect structures in small gaps

Ultrathin layer for forming a capacitive interface between joined integrated circuit component

Integrated interposer solutions for 2D and 3D IC packaging

Integrated circuit assemblies with reinforcement frames, and methods of manufacture

Polymer member based interconnect

Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture

Microelectronic assemblies formed using metal silicide, and methods of fabrication

Polymer member based interconnect

Integrated interposer solutions for 2D and 3D IC packaging

Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates

HD color imaging using monochromatic CMOS image sensors integrated in 3D package

Structures and methods for reliable packages

Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates

MOTOROLA INC

Method for forming a transistor having silicided regions

Conductive interconnect structure and method of formation

Method of forming conductive interconnect structure

Method for forming self-aligned silicide in a semiconductor device using vapor phase reaction

Process for forming a semiconductor device

Contact structure and process for formation

Method of making a contact structure

Process for forming a semiconductor device and a static-random-access memory cell

ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC

Stacked dies and methods for forming bonded structures

Stacked dies and methods for forming bonded structures

Stacked dies and methods for forming bonded structures

Bonded structures

Stacked dies and methods for forming bonded structures

Bonded structures

Bonded structure including an obstructive element directly bonded to a semiconductor element without an adhesive

Sealed bonded structures and methods for forming the same

INVENSAS BONDING TECH INC

Bonded structures

Stacked dies and methods for forming bonded structures

Bonded structures

Stacked dies and methods for forming bonded structures

Bonded structures

Bonded structures

Bonded structures

INVENSAS LLC

Capacitive coupling in a direct-bonded interface for microelectronic devices

ADEIA SEMICONDUCTOR TECH LLC

Capacitive coupling in a direct-bonded interface for microelectronic devices