Inventor

LEE CHUNG-YUAN

TW51 patents

⚠️ This page may combine multiple inventors who share the name “LEE CHUNG-YUAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE CHUNG-YUAN

NANYA TECHNOLOGY CORP

Method of fabricating shallow trench isolation

Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same

Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same

DRAM structure and method of making the same

Method of etching bottle trench and fabricating capacitor with same

Method for forming recesses

Method for forming a silicon nitride layer

Method for forming bottle trenches by liquid phase oxide deposition

Shallow trench isolation having an etching stop layer and method for fabricating same

Metal gate with composite film stack

Electrical device and method for fabricating the same

Method for forming a memory device with a recessed gate

Electrical device and method for fabricating the same

Method for forming recesses

Semiconductor structure

Dual damascene process

Method for forming a memory device with a recessed gate

Checkerboard deep trench dynamic random access memory cell array layout

Method of forming a vertical memory device with a rectangular trench

Method for fabricating trench isolation

Memory device with a length-controllable channel

Method for forming surface strap

UNITED MICROELECTRONICS CORP

Complementary LVTSCR ESD protection circuit for sub-micron CMOS integrated circuits

CMOS on-chip ESD protection circuit and semiconductor structure

Multiple well device and process of manufacture

Low-voltage gate trigger SCR (LVGTSCR) ESD protection circuit for input and output pads

Complementary-SCR electrostatic discharge protection circuit

CMOS on-chip ESD protection circuit and semiconductor structure

Metal oxide semiconductor device integral with an electro-static discharge circuit

Mask set and method for fabricating semiconductor device by using the same

Method of making a blanket N-well structure for SRAM data stability in P-type substrates

Process for fabricating a triple-well structure for semiconductor integrated circuit devices

Method for prevention of latch-up of CMOS devices

Metal oxide semiconductor device for an electro-static discharge circuit

Semiconductor device

Semiconductor device

Semiconductor device

Trim circuit for e-fuse

INOTERA MEMORIES INC

Method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning

Semiconductor structure

Vertical PMOS field effect transistor and manufacturing method thereof

Semiconductor layout structure

Memory unit, memory unit array and method of manufacturing the same

Semiconductor device and manufacturing method therefor

LEE TZUNG HAN

Vertical transistor for random-access memory and manufacturing method thereof

HUANG CHIH-WEI

Method of patterning metal alloy material layer having hafnium and molybdenum

LAN YUAN KU

Method for detecting errors of exposed positions of a pre-layer and a current layer by an integrated alignment and overlay mark

LEE TZUNG-HAN

Memory structure having a floating body and method for fabricating the same

CHEN HSIN-HUEI

Vertical PMOS field effect transistor and manufacturing method thereof

CHEN CHIEN WEI

Method of using NC-MRA to generate pelvic veins images and measure rate of blood flow