Inventor
ORENSTEIN DORON
IL30 patents
⚠️ This page may combine multiple inventors who share the name “ORENSTEIN DORON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
24 patentsUS7437581B2Oct 14, 2008
Method and apparatus for varying energy per instruction according to the amount of available parallelism
INTEL CORP138 citations97
US6557083B1Apr 29, 2003
Memory system for multiple data types
INTEL CORP102 citations97
US5835748ANov 10, 1998
Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file
INTEL CORP114 citations97
US6944720B2Sep 13, 2005
Memory system for multiple data types
INTEL CORP46 citations96
US5450605ASep 12, 1995
Boundary markers for indicating the boundary of a variable length instruction to facilitate parallel processing of sequential instructions
INTEL CORP60 citations95
US9672034B2Jun 6, 2017
Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits
INTEL CORP17 citations93
US6886105B2Apr 26, 2005
Method and apparatus for resuming memory operations from a low latency wake-up low power state
INTEL CORP23 citations92
US6580427B1Jun 17, 2003
Z-compression mechanism
INTEL CORP43 citations92
US5787026AJul 28, 1998
Method and apparatus for providing memory access in a processor pipeline
INTEL CORP21 citations91
US7051227B2May 23, 2006
Method and apparatus for reducing clock frequency during low workload periods
INTEL CORP23 citations90
US6724391B1Apr 20, 2004
Mechanism for implementing Z-compression transparently
INTEL CORP21 citations89
US7849465B2Dec 7, 2010
Programmable event driven yield mechanism which may activate service threads
INTEL CORP18 citations83
US7721129B2May 18, 2010
Method and apparatus for reducing clock frequency during low workload periods
INTEL CORP8 citations81
US11048507B2Jun 29, 2021
Compressed instruction format
INTEL CORP0 citations62
US7844801B2Nov 30, 2010
Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors
INTEL CORP2 citations61
US10831477B2Nov 10, 2020
In-lane vector shuffle instructions
INTEL CORP0 citations52
US10514916B2Dec 24, 2019
In-lane vector shuffle instructions
INTEL CORP0 citations52
US10514917B2Dec 24, 2019
In-lane vector shuffle instructions
INTEL CORP0 citations52
US10514918B2Dec 24, 2019
In-lane vector shuffle instructions
INTEL CORP0 citations52
US10509652B2Dec 17, 2019
In-lane vector shuffle instructions
INTEL CORP0 citations52
US10095515B2Oct 9, 2018
Compressed instruction format
INTEL CORP0 citations52
US9235415B2Jan 12, 2016
Permute operations with flexible zero control
INTEL CORP0 citations51
US8756403B2Jun 17, 2014
Compressed instruction format
INTEL CORP0 citations51
US9081562B2Jul 14, 2015
Unpacking packed data in multiple lanes
INTEL CORP1 citations48
SPERBER ZEEV
2 patentsUS8914613B2Dec 16, 2014
Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits
SPERBER ZEEV22 citations92
US8078836B2Dec 13, 2011
Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits
SPERBER ZEEV21 citations92