Inventor

STAMPER ANTHONY KENDALL

US58 patents

⚠️ This page may combine multiple inventors who share the name “STAMPER ANTHONY KENDALL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STAMPER ANTHONY KENDALL

IBM

Reduced electromigration and stressed induced migration of Cu wires by surface coating

Dual wired integrated circuit chips

Electrically tunable on-chip resistor

Process of making a microcavity structure and applications thereof

Through wafer via and method of making same

Double-sided integrated circuit chips

Low resistance and inductance backside through vias and methods of fabricating same

Double-sided integrated circuit chips

Low resistance and inductance backside through vias and methods of fabricating same

One-mask metal-insulator-metal capacitor and method for forming same

Integration of a MIM capacitor with a plate formed in a well region and with a high-k dielectric

Plasma treatment to enhance inorganic dielectric adhesion to copper

Annular damascene vertical natural capacitor

Through wafer vias and method of making same

Dual wired integrated circuit chips

Integration circuits for reducing electromigration effect

Dual-sided chip attached modules

Method for making a finger capacitor with tuneable dielectric constant

Dual damascene horn antenna

Dual wired integrated circuit chips

One-mask metal-insulator-metal capacitor and method for forming same

Specially shaped contact via and integrated circuit therewith

Double-sided integrated circuit chips

Post last wiring level inductor using patterned plate process

Post last wiring level inductor using patterned plate process

Post last wiring level inductor using patterned plate process

Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric material

Plasma treatment to enhance inorganic dielectric adhesion to copper

Structures including integrated circuits for reducing electromigration effect

Dual wired integrated circuit chips

Interconnect layers without electromigration

Post last wiring level inductor using patterned plate process

Shallow and deep trench isolation structures in semiconductor integrated circuits

Interconnect layers without electromigration

Through substrate annular via including plug filler

Through substrate via including variable sidewall profile

By-product collecting processes for cleaning processes

Method of forming a low stress polycide conductors on a semiconductor chip

FAYAZ MOHAMMED FAZIL

Methods and structures for controlling wafer curvature

Methods for controlling wafer curvature

DING HANYI

Through wafer vias and method of making same

Through wafer vias and method of making same

GLOBALFOUNDRIES INC

Gallium nitride (GaN) power amplifiers (PA) with angled electrodes and 100 CMOS and method for producing the same

Curvilinear wiring structure to reduce areas of high field density in an integrated circuit

BERNSTEIN KERRY

Double-sided integrated circuit chips

Double-sided integrated circuit chips

ANDERSON FELIX PATRICK

Curvilinear wiring structure to reduce areas of high field density in an integrated circuit

Fuse and pad stress relief

GLOBALFOUNDRIES SG PTE LTD

Monolithic integration of MEMS and IC devices

DUNN JAMES STUART

Tapered via and MIM capacitor