Inventor

RATH DAVID L

US69 patents

⚠️ This page may combine multiple inventors who share the name “RATH DAVID L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RATH DAVID L

IBM

Interconnect structures with fully aligned vias

Copper recess process with application to selective capping and electroless plating

Removal of dielectric oxides

Control of gas content in process liquids for improved megasonic cleaning of semiconductor wafers and microelectronics substrates

Selective and non-selective barrier layer wet removal

Structure and method of chemically formed anchored metallic vias

Copper recess process with application to selective capping and electroless plating

Selective etching of silicate

Method for cleaning semiconductor devices

Selective removal of etching residues

Removal of silicon oxide

Etching of silicon nitride

Process for removing etching residues, etching mask and silicon nitride and/or silicon dioxide

Etching of silicon nitride

Method for cleaning semiconductor devices

Apparatus and method for wet cleaning

Inductive head lamination with layer of magnetic quenching material

Semiconductor device formed by wet etch removal of Ru selective to other metals

Selective and non-selective barrier layer wet removal

Interconnect structures with fully aligned vias

Selective and non-selective barrier layer wet removal

Enhanced defect reduction for heteroepitaxy by seed shape engineering

Method for fabricating self-aligned nanostructure using self-assembly block copolymers, and structures fabricated therefrom

Method for isotropic etching of copper

Method for analyzing pH titration data

Maintaining uniform CMP hard mask thickness

Air gap structure having protective metal silicide pads on a metal feature

Stabilization of fluorine-containing dielectric materials in a metal insulator wiring structure

Low aspect ratio interconnect

Interconnect structures with fully aligned vias

Enhanced defect reduction for heteroepitaxy by seed shape engineering

Barrier planarization for interconnect metallization

Patterning magnetic films using self-stop electro-etching

Processes for uniform metal semiconductor alloy formation for front side contact metallization and photovoltaic device formed therefrom

Self-aligned mask to reduce cell layout area

Composition and coating to prevent current induced electrochemical dendrite formation between conductors on dielectric substrate

Additive core subtractive liner for metal cut etch processes

Metal surface protection

Transmon qubits with self defined junctions

Microfabricated air bridges for quantum circuits

Selective etch chemistry for gate electrode materials

Method for kinetically controlled etching of copper

Air gap structure having protective metal silicide pads on a metal feature

Oxidant and passivant composition and method for use in treating a microelectronic structure

High throughput insulation of 3D in-silicon high volumetric energy and power dense energy storage devices

CHEN KUAN-NENG

Bonding of substrates including metal-dielectric patterns with metal raised above dielectric and structures so formed

Bonding of substrates including metal-dielectric patterns with metal raised above dielectric

BRUCE ROBERT L

Homogeneous porous low dielectric constant materials

FISHER KATHRYN C

Processes for uniform metal semiconductor alloy formation for front side contact metallization and photovoltaic device formed therefrom

FITZSIMMONS JOHN A

Titanium-nitride removal