Inventor

CHAN YUEN H

US64 patents

⚠️ This page may combine multiple inventors who share the name “CHAN YUEN H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAN YUEN H

IBM

Row circuit ring oscillator method for evaluating memory cell performance

Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories

SRAM ring oscillator

Random access memory RAM employing complementary transistor switch (CTS) memory cells

Ring oscillator row circuit for evaluating memory cell performance

Local bit select with suppression of fast read before write

Method to improve cache capacity of SOI and bulk

Coupled body contacts for SOI differential circuits

Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories

High performance dual-stage sense amplifier circuit

Merged MISR and output register without performance impact for circuits under test

SRAM array with improved cell stability

Global bit select circuit with dual read and write bit line pairs

Clock driver and boundary latch for a multi-port SRAM

High performance programmable array local clock generator

Integrated circuit chip with improved array stability

Eight transistor SRAM cell with improved stability requiring only one word line

Merged MISR and output register without performance impact for circuits under test

Eight transistor SRAM cell with improved stability requiring only one word line

Method of converting short duration input pulses to longer duration output pulses

Self-resetting CMOS multiplexer with static output driver

Bit decoder for generating select and restore signals simultaneously

Word decoder for a memory array

High speed push-pull driver having current mirror pull-down

Global bit select circuit interface with dual read and write bit line pairs

Split L2 latch with glitch free programmable delay

Global bit line restore timing scheme and circuit

Global bit line restore timing scheme and circuit

CMOS sense amplifier

Means for enhancing logic circuit performance

Voltage burn-in scheme for BICMOS circuits

Asymmetrical clock chopper delay circuit

Random access memory RAM employing complementary transistor switch (CTS) memory cells

Integrated circuit chip with improved array stability

SRAM supply voltage global bitline precharge pulse

Random access memory employing complementary transistor switch (CTS) memory cells

Voltage mode operation scheme for bipolar arrays

Cache late select circuit

Programmable sense amplifier timing generator

Enhanced programmable pulsewidth modulating circuit for array clock generation

SRAM and dual single ended bit sense for an SRAM

High performance pseudo dynamic pulse controllable multiplexer

Programmable voltage divider

Programmable local clock buffer capable of varying initial settings

Difference signal path test and characterization circuit

CHAN YUEN H

Dual beta ratio SRAM

Low power programmable clock delay generator with integrated decode function

Global bit line restore by most significant bit of an address line

Single clock dynamic compare circuit

BUNCE PAUL A

Programmable control clock circuit including scan mode