Inventor

PLASS DONALD W

US54 patents

⚠️ This page may combine multiple inventors who share the name “PLASS DONALD W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PLASS DONALD W

IBM

Method and apparatus for implementing multiple column redundancy for memory

Efficient method of test and soft repair of SRAM with redundancy

Write control circuitry and method for a memory array configured with multiple memory subarrays

SRAM array with improved cell stability

Global and local read control synchronization method and system for a memory array configured with multiple memory subarrays

Memory output timing control circuit with merged functions

Protection of secure electronic modules against attacks

Efficient memory product for test and soft repair of SRAM with redundancy

Integrated circuit chip with improved array stability

Eight transistor SRAM cell with improved stability requiring only one word line

Eight transistor SRAM cell with improved stability requiring only one word line

Write driver circuit for memory array

MESFET sram with power saving current-limiting transistors

Write control circuitry and method for a memory array configured with multiple memory subarrays

Fast pulse powered NOR decode apparatus for semiconductor devices

High density bitline selection apparatus for semiconductor memory devices

SOI cell stability test method

Bias-controlled bit-line sensing scheme for eDRAM

Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of SRAM with redundancy

Bit-line mux driver with diode header for computer memory

Voltage bitline high (VBLH) regulation for computer memory

Integrated circuit chip with improved array stability

Method and apparatus for address generation

Programmable analog control of a bitline evaluation circuit

System and method for synchronizing memory array signals

Method for skip over redundancy decode with very low overhead

High speed latch and compare function

System for implementing a column redundancy scheme for arrays with controls that span multiple data bits

Charge pump generator with direct voltage sensor

Dynamic cascode-managed high-voltage word-line driver circuit

Write control method for a memory array configured with multiple memory subarrays

Clock control method and apparatus for a memory array

Apparatus and method for implementing multiple memory redundancy with delay tracking clock

Negative voltage generation for computer memory

Voltage comparator circuit and usage thereof

Integrated circuit chip with improved array stability

Method for enabling scan of defective ram prior to repair

Memory array with reduced circuitry

Dynamic high voltage driver with adjustable clamped output level

Dynamic cascode-managed high-voltage word-line driver circuit

ABIST data compression and serialization for memory built-in self test of SRAM with redundancy

Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steering

SRAM restore tracking circuit and method

Voltage comparator circuit and usage thereof

GLOBALFOUNDRIES INC

Gated-feedback sense amplifier for single-ended local bit-line memories

Charge pump generator with direct voltage sensor

REOHR WILLIAM ROBERT

High voltage word line driver

DAWSON JAMES W

Systems and methods for memory device precharging

BARTH JR JOHN E

Sense amplifier having an isolated pre-charge architecture, a memory circuit incorporating such a sense amplifier and associated methods

HWANG CHARLIE C

System to improve a multistage charge pump and associated methods