Inventor
CLARKE PHILIP
GB17 patents
⚠️ This page may combine multiple inventors who share the name “CLARKE PHILIP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
12 patentsUS7983094B1Jul 19, 2011
PVT compensated auto-calibration scheme for DDR3
ALTERA CORP49 citations97
US7590008B1Sep 15, 2009
PVT compensated auto-calibration scheme for DDR3
ALTERA CORP58 citations97
US7593273B2Sep 22, 2009
Read-leveling implementations for DDR3 applications on an FPGA
ALTERA CORP44 citations95
US7928770B1Apr 19, 2011
I/O block for high performance memory interfaces
ALTERA CORP22 citations92
US7990786B2Aug 2, 2011
Read-leveling implementations for DDR3 applications on an FPGA
ALTERA CORP6 citations73
US7589556B1Sep 15, 2009
Dynamic control of memory interface timing
ALTERA CORP7 citations73
US7642812B1Jan 5, 2010
Distribution and synchronization of a divided clock signal
ALTERA CORP4 citations63
US7990783B1Aug 2, 2011
Postamble timing for DDR memories
ALTERA CORP3 citations62
US7876630B1Jan 25, 2011
Postamble timing for DDR memories
ALTERA CORP4 citations62
US7791375B1Sep 7, 2010
DQS re sync calibration
ALTERA CORP5 citations62
US7688116B1Mar 30, 2010
Read data path
ALTERA CORP3 citations54
US7898296B1Mar 1, 2011
Distribution and synchronization of a divided clock signal
ALTERA CORP0 citations52