Inventor
NEVES JOSE L
US15 patents
⚠️ This page may combine multiple inventors who share the name “NEVES JOSE L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
13 patentsUS7376924B2May 20, 2008
Methods for placement which maintain optimized behavior, while improving wireability potential
IBM10 citations83
US7356793B2Apr 8, 2008
Genie: a method for classification and graphical display of negative slack timing test failures
IBM9 citations82
US7921398B2Apr 5, 2011
System and medium for placement which maintain optimized timing behavior, while improving wireability potential
IBM6 citations73
US7810062B2Oct 5, 2010
Method for eliminating negative slack in a netlist via transformation and slack categorization
IBM7 citations72
US9934341B2Apr 3, 2018
Simulation of modifications to microprocessor design
IBM2 citations69
US7823108B2Oct 26, 2010
Chip having timing analysis of paths performed within the chip during the design process
IBM5 citations58
US7831946B2Nov 9, 2010
Clock distribution network wiring structure
IBM5 citations56
US9734270B2Aug 15, 2017
Control path power adjustment for chip design
IBM0 citations51
US9703910B2Jul 11, 2017
Control path power adjustment for chip design
IBM0 citations51
US9256705B2Feb 9, 2016
Reducing repeater power
IBM0 citations51
US10169526B2Jan 1, 2019
Incremental parasitic extraction for coupled timing and power optimization
IBM0 citations49
US9858383B2Jan 2, 2018
Incremental parasitic extraction for coupled timing and power optimization
IBM1 citations49
US9928322B2Mar 27, 2018
Simulation of modifications to microprocessor design
IBM0 citations48