Inventor
SUBBANNAVAR BADARISH MOHAN
IN11 patents
Patents
11 patentsUS9350327B2May 24, 2016
Flip-flops with low clock power
TEXAS INSTRUMENTS INC9 citations82
US9246489B1Jan 26, 2016
Integrated clock gating cell using a low area and a low power latch
TEXAS INSTRUMENTS INC13 citations82
US7825689B1Nov 2, 2010
Functional-input sequential circuit
TEXAS INSTRUMENTS INC12 citations79
US10382020B2Aug 13, 2019
Ultra-low power static state flip flop
TEXAS INSTRUMENTS INC3 citations71
US10056882B2Aug 21, 2018
Ultra-low power static state flip flop
TEXAS INSTRUMENTS INC3 citations71
US9425771B2Aug 23, 2016
Low area flip-flop with a shared inverter
TEXAS INSTRUMENTS INC6 citations71
US11043937B1Jun 22, 2021
Reduced area, reduced power flip-flop
TEXAS INSTRUMENTS INC4 citations70
US11509294B2Nov 22, 2022
Reduced area, reduced power flip-flop
TEXAS INSTRUMENTS INC0 citations59
US9471278B2Oct 18, 2016
Low area full adder with shared transistors
TEXAS INSTRUMENTS INC1 citations50
US12211850B2Jan 28, 2025
Cell architecture with extended transistor geometry
TEXAS INSTRUMENTS INC0 citations41
US11626879B2Apr 11, 2023
Integrated circuit including a combined logic cell
TEXAS INSTRUMENTS INC0 citations41