Inventor

GERHARDT MARTIN

DE23 patents

⚠️ This page may combine multiple inventors who share the name “GERHARDT MARTIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GERHARDT MARTIN

GLOBALFOUNDRIES INC

Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy

Technique for enhancing transistor performance by transistor specific contact design

Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell and method for the formation thereof

OPC enlarged dummy electrode to eliminate ski slope at eSiGe

Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel region

Method of increasing transistor drive current by recessing an isolation trench

Transistor element with reduced lateral electrical field

Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell

Method for forming a strained transistor by stress memorization based on a stressed implantation mask

Transistor devices with high-k insulation layers

Technique for manufacturing semiconductor devices comprising transistors with different threshold voltages

Heat dissipative element for polysilicon resistor bank

ADVANCED MICRO DEVICES INC

Technique for transferring strain into a semiconductor region

Methods for fabricating a stressed MOS device

Methods for fabricating a CMOS device including silicide contacts

Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device

GERHARDT MARTIN

Methods of forming transistor devices with high-k insulation layers and the resulting devices

Technique for enhancing transistor performance by transistor specific contact design

Shallow source and drain architecture in an active region of a semiconductor device having a pronounced surface topography by tilted implantation

Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography

IBM

Process and system for automatic, computer-system-supported optimisation

WIRBELEIT FRANK

Method for forming a strained transistor by stress memorization based on a stressed implantation mask

BSH HAUSGERAETE GMBH

Circuit arrangement for controlling a plurality of electrical loads