Inventor

JENG ERIK S

TW76 patents

⚠️ This page may combine multiple inventors who share the name “JENG ERIK S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JENG ERIK S

VANGUARD INT SEMICONDUCT CORP

Method for simultaneously fabricating a DRAM capacitor and metal interconnections

Method for simultaneously forming capacitor plate and metal contact structures for a high density DRAM device

Method for fabricating high density integrated circuits using oxide and polysilicon spacers

Method for manufacturing crown-shaped capacitors for dynamic random access memory integrated circuits

Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections

Method for fabricating dynamic random access memory (DRAM) by simultaneous formation of tungsten bit lines and tungsten landing plug contacts

Method for fabricating capacitor-under-bit line (CUB) dynamic random access memory (DRAM) using tungsten landing plug contacts

Two step plasma etch method for forming self aligned contact

Method for fabricating capacitor-over-bit-line dynamic random access memory (DRAM) using self-aligned contact etching technology

Method of forming an isolation region in a semiconductor substrate

Method for manufacturing double-crown capacitors self-aligned to node contacts on dynamic random access memory

Method for forming interconnections and conductors for high density integrated circuits

Method of fabricating single crown, extendible to triple crown, stacked capacitor structures, using a self-aligned capacitor node contact

Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections

Method for fabricating interconnection and capacitors of a DRAM using a simple geometry active area, self-aligned etching, and polysilicon plugs

Method for improving patterning of a conductive layer in an integrated circuit

LDD spacers in MOS devices with double spacers

Stacked capacitor DRAM structure featuring a multiple crown shaped polysilicon lower electrode

Method for fabricating vertical fin capacitor structures

Method of fabricating LDD spacers in MOS devices with double spacers and device manufactured thereby

Method for fabricating a four fin capacitor structure

Method for fabricating interconnecting lines and contacts using conformal deposition

High density integrated circuits using tapered and self-aligned contacts

Method for forming self-aligned contacts using a hard mask

Method of self-aligned contact hole etching by fluorine-containing discharges

Method of fabricating a capacitor under bit line DRAM structure using contact hole liners

Method for fabricating crown-shaped capacitor structures

Method of forming a cob dram by using self-aligned node and bit line contact plug

Method for eliminating CMP induced microscratches

Method for fabricating ultra-small interconnections using simplified patterns and sidewall contact plugs

Method for forming multi-level contacts using a H-containing fluorocarbon chemistry

Method of fabricating contact holes in high density integrated circuits using polysilicon landing plug and self-aligned etching processes

Method of fabricating a shallow trench isolation by using oxide/oxynitride layers

Method for fabricating reduced contacts using retardation layers

Method for controlling linewidth by etching bottom anti-reflective coating

Method for etching high aspect-ratio multilevel contacts

Method of fabricating a self-aligned contact

Method for forming a semiconductor device

Method of dry etching A1Cu using SiN hard mask

Multiple etch contact etching method incorporating post contact etch etching

Method of fabricating sidewall spacers for a self-aligned contact hole

Method for forming a capacitor using a silicon oxynitride etching stop layer

Etching process

Method for forming self-aligned contact with liner

Method of forming a contact hole in a semiconductor device

APPLIED INTELLECTUAL PROPERTIE

Nonvolatile memory capable of storing multibits binary information and the method of forming the same

Nonvolatile memory capable of storing multibits binary information and the method of forming the same

Nonvolatile memory with undercut trapping structure

Nonvolatile memory with spacer trapping structure

VANGAURD INTERNATIONAL SEMICON

Method of fabricating high density integrated circuits, containing stacked capacitor DRAM devices, using elevated trench isolation and isolation spacers