Inventor

KU JA-HUM

KR44 patents

⚠️ This page may combine multiple inventors who share the name “KU JA-HUM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KU JA-HUM

SAMSUNG ELECTRONICS CO LTD

Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer

Methods for forming self-aligned dual stress liners for CMOS semiconductor devices

Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby

Methods for forming damascene wiring structures having line and plug conductors formed from different materials

Methods of fabricating a semiconductor device having MOS transistor with strained channel

Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer

HDP/PECVD methods of fabricating stress nitride structures for field effect transistors

Methods of fabricating semiconductor devices having a dual stress liner

Method of forming self-aligned silicide in semiconductor device

Method of forming cobalt silicide film and method of manufacturing semiconductor device having cobalt silicide film

Integrated circuit device and method of manufacturing the same

Semiconductor wafer having embedded electroplating current paths to provide uniform plating over wafer surface

Nickel alloy salicide transistor structure and method for manufacturing same

Method of forming a metal gate electrode

Method of fabricating semiconductor device having metal conducting layer

Transistor having reverse self-aligned structure

Integrated circuit device and method of manufacturing the same

Methods of fabricating a semiconductor device having a metal gate pattern

Nickel salicide process with reduced dopant deactivation

Semiconductor device including contact plug and method of manufacturing the same

Method of forming a metal gate

Methods of forming CMOS integrated circuits that utilize insulating layers with high stress characteristics to improve NMOS and PMOS transistor carrier mobilities

Test structure of semiconductor device

Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics

CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein

Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniques

Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive material layer

Methods of forming integrated circuit devices having metal interconnect structures therein

Methods of fabricating a semiconductor device having a metal gate pattern

Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive material layer

Methods for forming contacts for dual stress liner CMOS semiconductor devices

Test structure of semiconductor device

Method for fabricating semiconductor device using a nickel salicide process

Devices and methods for constructing electrically programmable integrated fuses for low power applications

Method for fabricating MOS semiconductor device having salicide region and LDD structure

Methods of fabricating semiconductor device having a metal gate pattern

Methods of fabricating integrated circuit gates by pretreating prior to oxidizing

Methods of forming a semiconductor device having a metal gate electrode and associated devices

Methods for removing gate sidewall spacers in CMOS semiconductor fabrication processes

PARK HONG-BAE

Integrated circuit device and method of manufacturing the same

SAMSUNG ELECTRONICS LTD CO

Methods of fabricating a semiconductor device having a metal gate pattern

INFINEON TECHNOLOGIES AG

Method and apparatus for manufacturing a semiconductor

IBM

Silicided polysilicon spacer for enhanced contact area

HAN CHANG-HO

Method of calibrating target values and processing systems configured to calibrate the target values