Inventor

SUN MIN-CHUL

KR33 patents

⚠️ This page may combine multiple inventors who share the name “SUN MIN-CHUL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SUN MIN-CHUL

SAMSUNG ELECTRONICS CO LTD

Semiconductor integrated test structures for electron beam inspection of semiconductor wafers

Methods of fabricating a semiconductor device having MOS transistor with strained channel

Semiconductor device

Semiconductor device with nanowires in different regions at different heights

Semiconductor device with nanowires in different regions at different heights and fabricating method thereof

Nickel alloy salicide transistor structure and method for manufacturing same

Method of fabricating semiconductor device having metal conducting layer

Methods of manufacturing semiconductor devices by etching active fins using etching masks

Semiconductor devices having vertical device and non-vertical device and methods of forming the same

Nickel salicide process with reduced dopant deactivation

Semiconductor device including isolation regions

Semiconductor device including isolation regions

Test structure of semiconductor device

Differential mechanical stress-producing regions for integrated circuit field effect transistors

Methods of manufacturing semiconductor devices by etching active fins using etching masks and forming source/drain layers on the active fins

Methods of manufacturing semiconductor devices by etching active fins using etching masks

Methods of manufacturing semiconductor devices by etching active fins using etching masks

Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive material layer

Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive material layer

Semiconductor device including isolation regions

Semiconductor device including isolation regions

Semiconductor device including isolation regions

Test structure of semiconductor device

Methods of manufacturing finFET semiconductor devices

Method for fabricating semiconductor device

Semiconductor device and method for fabricating the same

Gate structure

Methods for removing gate sidewall spacers in CMOS semiconductor fabrication processes

SUN MIN-CHUL

Semiconductor devices having vertical device and non-vertical device and methods of forming the same

Field-effect transistor having back gate and method of fabricating the same

Method of fabricating semiconductor device having buried wiring and related device

Methods of fabricating semiconductor device using high-K layer for spacer etch stop and related devices

IBM

Structure and method of mapping signal intensity to surface voltage for integrated circuit inspection