Inventor
JOHNSON FRANK SCOTT
US24 patents
⚠️ This page may combine multiple inventors who share the name “JOHNSON FRANK SCOTT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
GLOBALFOUNDRIES INC
7 patentsUS8383503B2Feb 26, 2013
Methods for forming semiconductor structures using selectively-formed sidewall spacers
GLOBALFOUNDRIES INC16 citations92
US8039326B2Oct 18, 2011
Methods for fabricating bulk FinFET devices having deep trench isolation
GLOBALFOUNDRIES INC31 citations92
US7960287B2Jun 14, 2011
Methods for fabricating FinFET structures having different channel lengths
GLOBALFOUNDRIES INC25 citations92
US8039349B2Oct 18, 2011
Methods for fabricating non-planar semiconductor devices having stress memory
GLOBALFOUNDRIES INC9 citations84
US8030144B2Oct 4, 2011
Semiconductor device with stressed fin sections, and related fabrication methods
GLOBALFOUNDRIES INC7 citations84
US7977174B2Jul 12, 2011
FinFET structures with stress-inducing source/drain-forming spacers and methods for fabricating the same
GLOBALFOUNDRIES INC11 citations84
US7985639B2Jul 26, 2011
Method for fabricating a semiconductor device having a semiconductive resistor structure
GLOBALFOUNDRIES INC8 citations83
TEXAS INSTRUMENTS INC
6 patentsUS7930656B2Apr 19, 2011
System and method for making photomasks
TEXAS INSTRUMENTS INC8 citations80
US7763540B2Jul 27, 2010
Method of forming a silicided gate utilizing a CMP stack
TEXAS INSTRUMENTS INC5 citations63
US7910422B2Mar 22, 2011
Reducing gate CD bias in CMOS processing
TEXAS INSTRUMENTS INC5 citations62
US6130122AOct 10, 2000
Method for forming a BiCMOS integrated circuit with Nwell compensation implant and method
TEXAS INSTRUMENTS INC5 citations62
US6797577B2Sep 28, 2004
One mask PNP (or NPN) transistor allowing high performance
TEXAS INSTRUMENTS INC3 citations56
US7785970B2Aug 31, 2010
Method of forming source and drain regions utilizing dual capping layers and split thermal processes
TEXAS INSTRUMENTS INC0 citations42
JOHNSON FRANK SCOTT
3 patentsUS8729609B2May 20, 2014
Integrated circuits including multi-gate transistors locally interconnected by continuous fin structure and methods for the fabrication thereof
JOHNSON FRANK SCOTT10 citations82
US8865596B2Oct 21, 2014
Methods for forming semiconductor structures using selectively-formed sidewall spacers
JOHNSON FRANK SCOTT3 citations61
US8192641B2Jun 5, 2012
Methods for fabricating non-planar electronic devices having sidewall spacers formed adjacent selected surfaces
JOHNSON FRANK SCOTT4 citations61