Inventor
GAMBINO JEFFREY PETER
US92 patents
⚠️ This page may combine multiple inventors who share the name “GAMBINO JEFFREY PETER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
44 patentsUS7193423B1Mar 20, 2007
Wafer-to-wafer alignments
IBM231 citations98
US7285477B1Oct 23, 2007
Dual wired integrated circuit chips
IBM49 citations96
US5876788AMar 2, 1999
High dielectric TiO2 -SiN composite films for memory applications
IBM97 citations96
US6204532B1Mar 20, 2001
Pillar transistor incorporating a body contact
IBM51 citations94
US6200834B1Mar 13, 2001
Process for fabricating two different gate dielectric thicknesses using a polysilicon mask and chemical mechanical polishing (CMP) planarization
IBM50 citations93
US8013342B2Sep 6, 2011
Double-sided integrated circuit chips
IBM19 citations92
US7884475B2Feb 8, 2011
Conductor structure including manganese oxide capping layer
IBM24 citations92
US7670927B2Mar 2, 2010
Double-sided integrated circuit chips
IBM15 citations92
US7482675B2Jan 27, 2009
Probing pads in kerf area for wafer testing
IBM40 citations92
US7459785B2Dec 2, 2008
Electrical interconnection structure formation
IBM28 citations92
US7348210B2Mar 25, 2008
Post bump passivation for soft error protection
IBM25 citations92
US6548357B2Apr 15, 2003
Modified gate processing for optimized definition of array and logic devices on same chip
IBM28 citations92
US6403423B1Jun 11, 2002
Modified gate processing for optimized definition of array and logic devices on same chip
IBM38 citations92
US6261914B1Jul 17, 2001
Process for improving local uniformity of chemical mechanical polishing using a self-aligned polish rate enhancement layer
IBM21 citations92
US6084276AJul 4, 2000
Threshold voltage tailoring of corner of MOSFET device
IBM32 citations92
US6013583AJan 11, 2000
Low temperature BPSG deposition process
IBM50 citations92
US5994202ANov 30, 1999
Threshold voltage tailoring of the corner of a MOSFET device
IBM24 citations92
US5759867AJun 2, 1998
Method of making a disposable corner etch stop-spacer for borderless contacts
IBM23 citations92
US7781292B2Aug 24, 2010
High power device isolation and integration
IBM22 citations91
US7524694B2Apr 28, 2009
Funneled light pipe for pixel sensors
IBM40 citations91
US6504210B1Jan 7, 2003
Fully encapsulated damascene gates for Gigabit DRAMs
IBM48 citations91
US6448173B1Sep 10, 2002
Aluminum-based metallization exhibiting reduced electromigration and method therefor
IBM21 citations91
US6020239AFeb 1, 2000
Pillar transistor incorporating a body contact
IBM25 citations90
US8361598B2Jan 29, 2013
Substrate anchor structure and method
IBM8 citations84
US7960245B2Jun 14, 2011
Dual wired integrated circuit chips
IBM12 citations84
US7935408B2May 3, 2011
Substrate anchor structure and method
IBM10 citations84
US7911803B2Mar 22, 2011
Current distribution structure and method
IBM7 citations84
US7859122B2Dec 28, 2010
Final via structures for bond pad-solder ball interconnections
IBM14 citations84
US7666746B2Feb 23, 2010
Semiconductor transistors having high-K gate dielectric layers, metal gate electrode regions, and low fringing capacitances
IBM9 citations84
US7462509B2Dec 9, 2008
Dual-sided chip attached modules
IBM10 citations84
US7256503B2Aug 14, 2007
Chip underfill in flip-chip technologies
IBM14 citations84
US6326260B1Dec 4, 2001
Gate prespacers for high density, high performance DRAMs
IBM16 citations83
US6014310AJan 11, 2000
High dielectric TiO2 -SiN composite films for memory applications
IBM14 citations81
US7939914B2May 10, 2011
Dual wired integrated circuit chips
IBM4 citations74
US5923991AJul 13, 1999
Methods to prevent divot formation in shallow trench isolation areas
IBM11 citations74
US7989312B2Aug 2, 2011
Double-sided integrated circuit chips
IBM6 citations73
US7790559B2Sep 7, 2010
Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes
IBM7 citations73
US7763954B2Jul 27, 2010
Post last wiring level inductor using patterned plate process
IBM7 citations73
US7741698B2Jun 22, 2010
Post last wiring level inductor using patterned plate process
IBM6 citations73
US7573117B2Aug 11, 2009
Post last wiring level inductor using patterned plate process
IBM7 citations73
US8004289B2Aug 23, 2011
Wafer-to-wafer alignments
IBM5 citations71
US7474104B2Jan 6, 2009
Wafer-to-wafer alignments
IBM5 citations68
US5882992AMar 16, 1999
Method for fabricating Tungsten local interconnections in high density CMOS circuits
IBM14 citations68
US5795826AAug 18, 1998
Method of chemically mechanically polishing an electronic component
IBM9 citations68
SEMICONDUCTOR COMPONENTS IND LLC
4 patentsUS10431614B2Oct 1, 2019
Edge seals for semiconductor packages
SEMICONDUCTOR COMPONENTS IND LLC21 citations92
US10090342B1Oct 2, 2018
Stacked image sensor capacitors and related methods
SEMICONDUCTOR COMPONENTS IND LLC40 citations91
US10403659B2Sep 3, 2019
Stacked image sensor capacitors and related methods
SEMICONDUCTOR COMPONENTS IND LLC8 citations81
US12034025B2Jul 9, 2024
Semiconductor devices with single-photon avalanche diodes and isolation structures
SEMICONDUCTOR COMPONENTS IND LLC2 citations70
ADKISSON JAMES WILLIAM
1 patentGAMBINO JEFFREY PETER
1 patentShowing the top 50 of 92 patents by PatentIndex Score.