Inventor

CHEN KUANG-CHAO

TW71 patents

⚠️ This page may combine multiple inventors who share the name “CHEN KUANG-CHAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN KUANG-CHAO

MACRONIX INT CO LTD

Pad and method for chemical mechanical polishing

Method for forming self-aligned contacts and local interconnects simultaneously

Method for forming self-aligned contacts and local interconnects simultaneously

Elimination of the fast-erase phenomena in flash memory

Integrated circuit device with layered trench conductors

Method for measuring and analyzing surface structure of chip or wafer

Cleaning method for use in semiconductor device fabrication

Word line structure and method of manufacturing the same

Apparatus and method for a non-volatile memory structure comprising a multi-layer silicon-rich, silicon nitride trapping layer

Method of manufacturing flash memory

Method of filling intervals and fabricating shallow trench isolation structures

Memory device with multi-layered charge storage stack

Method of detecting bitmap failure associated with physical coordinate

Method of fabricating flash memory

Method for fabrication a flash memory device having self-aligned contact

Method for fabricating memory device

Memory device and method for fabricating the same

Method of fabricating deep trench semiconductor devices, and deep trench semiconductor devices

Multi-layer polysilicon suppression of implant species penetration

Polishing pad and process of chemical mechanical use thereof

Methods for metal ARC layer formation

Semiconductor substrate and semiconductor device

Fabrication method of electronic device

Method for eliminating polycide voids through nitrogen implantation

Ultraviolet blocking layer

Method of fabricating semiconductor device

Semiconductor device and method of fabricating the same

Electron beam inspection optimization

HDP-CVD process, filling-in process utilizing HDP-CVD, and HDP-CVD system

Interconnection process

Method for detecting an electrical defect of contact/via plugs

MOSEL VITELIC INC

Teos-ozone planarization process

Method of forming a capacitor of a dram cell

Method for planarizing the interface of polysilicon and silicide in a polycide structure

Method for forming trenched polysilicon structure

Method for increasing utilizable surface of rugged polysilicon layer in semiconductor device

Method for using oxygen plasma treatment on a dielectric layer

IND TECH RES INST

Inter-metal-dielectric planarization process

Aluminum plug process

Blanket tungsten etchback process using disposable spin-on-glass

Spin-on-glass integration planarization having siloxane partial etchback and silicate processes

Submicron planarization process with passivation on metal line

MOSEL VITELLIC INC

Rugged stacked oxide layer structure and method of fabricating same

Method of fabricating a capacitor on a rugged stacked oxide layer

LUOH TUUNG

Semiconductor device having plural conductive layers disposed within dielectric layer

Multivariate monitoring method for plasma process machine

(unassigned)

Method for forming a VIA in an inter metal dielectric (IMD) containing spin on glass (SOG)

VANGUARD INT SEMICONDUCT CORP

High stress oxide to eliminate BPSG/SiN cracking

MACRONIOX INTERNAT CO LTD

Method for removing fences without reduction of ONO film thickness

CHENG MING-DA

Isolation structure, non-volatile memory having the same, and method of fabricating the same