Inventor
BOOTHROYD DONALD C
US14 patents
⚠️ This page may combine multiple inventors who share the name “BOOTHROYD DONALD C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
HONEYWELL INF SYSTEMS
8 patentsUS4583199AApr 15, 1986
Apparatus for aligning and packing a first operand into a second operand of a different character size
HONEYWELL INF SYSTEMS30 citations92
US4620274AOct 28, 1986
Data available indicator for an exhausted operand string
HONEYWELL INF SYSTEMS22 citations81
US4598365AJul 1, 1986
Pipelined decimal character execution unit
HONEYWELL INF SYSTEMS24 citations81
US4611278ASep 9, 1986
Wraparound buffer for repetitive decimal numeric operations
HONEYWELL INF SYSTEMS17 citations73
US4608633AAug 26, 1986
Method for decreasing execution time of numeric instructions
HONEYWELL INF SYSTEMS18 citations73
US4598359AJul 1, 1986
Apparatus for forward or reverse reading of multiple variable length operands
HONEYWELL INF SYSTEMS12 citations73
US4575795AMar 11, 1986
Apparatus for detecting a predetermined character of a data string
HONEYWELL INF SYSTEMS18 citations73
US4506345AMar 19, 1985
Data alignment circuit
HONEYWELL INF SYSTEMS5 citations62
BULL HN INFORMATION SYST
6 patentsUS5435000AJul 18, 1995
Central processing unit using dual basic processing units and combined result bus
BULL HN INFORMATION SYST46 citations90
US5251321AOct 5, 1993
Binary to binary coded decimal and binary coded decimal to binary conversion in a VLSI central processing unit
BULL HN INFORMATION SYST20 citations73
US5440724AAug 8, 1995
Central processing unit using dual basic processing units and combined result bus and incorporating means for obtaining access to internal BPU test signals
BULL HN INFORMATION SYST16 citations71
US5515529AMay 7, 1996
Central processor with duplicate basic processing units employing multiplexed data signals to reduce inter-unit conductor count
BULL HN INFORMATION SYST3 citations62
US5495579AFeb 27, 1996
Central processor with duplicate basic processing units employing multiplexed cache store control signals to reduce inter-unit conductor count
BULL HN INFORMATION SYST2 citations62
US5422837AJun 6, 1995
Apparatus for detecting differences between double precision results produced by dual processing units operating in parallel
BULL HN INFORMATION SYST4 citations60