Inventor

D INVERNO DOMINIQUE

FR30 patents

⚠️ This page may combine multiple inventors who share the name “D INVERNO DOMINIQUE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

D INVERNO DOMINIQUE

TEXAS INSTRUMENTS INC

Temperature field controlled scheduling for processing systems

JAVA DSP acceleration by byte-code optimization

Task based adaptative profiling and debugging

Dynamic hardware control for energy management systems using task attributes

Dynamic hardware configuration for energy management systems using task attributes

Multiple microprocessors with a shared cache

Software controlled cache configuration based on average miss rate

Priority arbitration based on current task and MMU

Interruptible and re-entrant cache clean range instruction

MMU descriptor having big/little endian bit to control the transfer data between devices

Master/slave processing system with shared translation lookaside buffer

System and method to automatically stack and unstack Java local variables

Tasks distribution in a multi-processor including a translation lookaside buffer shared between processors

Cache with selective write allocation

Processing system with shared translation lookaside buffer

Energy-aware scheduling of application execution

Memory allocation in a multi-processor system

Data processing apparatus, system and method

Management of stack-based memory usage in a processor

Stack register reference control bit in source operand of instruction

Saturated arithmetic in a processing unit

Cache coherency in a multi-processor system

Embedded garbage collection

Accessing device driver memory in programming language representation

Test and skip processor instruction having at least one register operand

Mixed stack-based RISC processor

Memory management of local variables

CHAUVEL GERARD

Dirty cache line write back policy based on stack size trend information

Micro-sequence based security model

Multi-processor computing system having a JAVA stack machine and a RISC-based processor