Inventor
BLAINEY ROBERT J
CA21 patents
⚠️ This page may combine multiple inventors who share the name “BLAINEY ROBERT J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
13 patentsUS7765534B2Jul 27, 2010
Compiler with cache utilization optimizations
IBM31 citations92
US5613121AMar 18, 1997
Method and system of generating combined storage references
IBM38 citations92
US8832669B2Sep 9, 2014
Compiling code for an enhanced application binary interface (ABI) with decode time instruction optimization
IBM9 citations83
US7140009B2Nov 21, 2006
Unrolling transformation of nested loops
IBM12 citations83
US8032736B2Oct 4, 2011
Methods, apparatus and articles of manufacture for regaining memory consistency after a trap via transactional memory
IBM12 citations81
US10389800B2Aug 20, 2019
Minimizing execution time of a compute workload based on adaptive complexity estimation
IBM9 citations79
US9396115B2Jul 19, 2016
Rewind only transactions in a data processing system supporting transactional storage accesses
IBM2 citations63
US6907509B2Jun 14, 2005
Automatic program restructuring to reduce average cache miss penalty
IBM6 citations59
US9268599B2Feb 23, 2016
Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memories
IBM0 citations49
US8380941B2Feb 19, 2013
Dynamic nest level determination for nested transactional memory rollback
IBM0 citations47
US9904922B2Feb 27, 2018
Efficient tail calculation to exploit data correlation
IBM0 citations43
US9892411B2Feb 13, 2018
Efficient tail calculation to exploit data correlation
IBM0 citations43
US9081607B2Jul 14, 2015
Conditional transaction abort and precise abort handling
IBM0 citations42
BLAINEY ROBERT J
7 patentsUS8607211B2Dec 10, 2013
Linking code for an enhanced application binary interface (ABI) with decode time instruction optimization
BLAINEY ROBERT J42 citations92
US8615745B2Dec 24, 2013
Compiling code for an enhanced application binary interface (ABI) with decode time instruction optimization
BLAINEY ROBERT J17 citations91
US8615746B2Dec 24, 2013
Compiling code for an enhanced application binary interface (ABI) with decode time instruction optimization
BLAINEY ROBERT J13 citations83
US9170844B2Oct 27, 2015
Prioritization for conflict arbitration in transactional memory management
BLAINEY ROBERT J5 citations70
US8612959B2Dec 17, 2013
Linking code for an enhanced application binary interface (ABI) with decode time instruction optimization
BLAINEY ROBERT J4 citations60
US9268598B2Feb 23, 2016
Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories
BLAINEY ROBERT J0 citations51
US8250315B2Aug 21, 2012
Dynamic nest level determination for nested transactional memory rollback
BLAINEY ROBERT J0 citations47