Inventor

PIETAMBARAM SRINIVAS

US60 patents

⚠️ This page may combine multiple inventors who share the name “PIETAMBARAM SRINIVAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PIETAMBARAM SRINIVAS

INTEL CORP

Hybrid fan-out architecture with EMIB and glass core for heterogeneous die integration applications

Electromigration resistant and profile consistent contact arrays

Chiplet first architecture for die tiling applications

Chiplet first architecture for die tiling applications

Chiplet first architecture for die tiling applications

Stretchable embedded electronic package

Heterogeneous nested interposer package for IC chips

Heterogeneous nested interposer package for IC chips

Thin film barrier seed metallization in magnetic-plugged through hole inductor

Electromigration resistant and profile consistent contact arrays

Surface finishes with low rBTV for fine and mixed bump pitch architectures

Bendable and stretchable electronic devices and methods

Enabling magnetic films in inductors integrated into semiconductor packages

Integrated circuit substrate and method of making

Chiplet first architecture for die tiling applications

Coreless electronic substrates having embedded inductors

Hybrid conductive vias for electronic substrates

Substrate embedded magnetic core inductors and method of making

Angled inductor with small form factor

Hybrid fan-out architecture with EMIB and glass core for heterogeneous die integration applications

Hybrid fan-out architecture with EMIB and glass core for heterogeneous die integration applications

Glass core patch with in situ fabricated fan-out layer to enable die tiling applications

Method to form high capacitance thin film capacitors (TFCs) as embedded passives in organic substrate packages

Patch accommodating embedded dies having different thicknesses

Hybrid fan-out architecture with EMIB and glass core for heterogeneous die integration applications

Sandwich-molded cores for high-inductance architectures

Substrate embedded magnetic core inductors and method of making

Techniques for an inductor at a first level interface

Techniques for an inductor at a second level interface

Techniques for an inductor at a second level interface

Patternable die attach materials and processes for patterning

Hybrid bonding technologies with thermal expansion compensation structures

Methods and apparatus to increase glass core thickness

Heterogeneous nested interposer package for IC chips

Electronic substrate having an embedded etch stop to control cavity depth in glass layers therein

Heterogeneous nested interposer package for IC chips

Hybrid glass core for wafer level and panel level packaging applications

Patternable die attach materials and processes for patterning

Conductive route patterning for electronic substrates

Dual-damascene zero-misalignment-via process for semiconductor packaging

Surface finishes with low RBTV for fine and mixed bump pitch architectures

Package architecture with tunable magnetic properties for embedded devices

Radio frequency antennas and waveguides for communication between integrated circuit devices

Optimization for raster scanning

Glass dielectric layer with patterning

Methods and apparatus to reduce defects in interconnects between semicondcutor dies and package substrates

Capacitors with nanoislands on conductive plates

EVERSPIN TECHNOLOGIES INC

Magnetic field sensor

Two-axis magnetic field sensor having reduced compensation angle for zero offset

SUN JIJUN

Two-axis magnetic field sensor having reduced compensation angle for zero offset