Inventor

PAPADOPOULOS GREGORY M

US16 patents

⚠️ This page may combine multiple inventors who share the name “PAPADOPOULOS GREGORY M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MASSACHUSETTS INST TECHNOLOGY

7 patents

US5560029ASep 24, 1996

Efficient data processor instrumentation for systematic program debugging and development

MASSACHUSETTS INST TECHNOLOGY33 citations92

US5386586AJan 31, 1995

System and method for construction of lists of deferred service requests

MASSACHUSETTS INST TECHNOLOGY6 citations62

INTEL CORP

4 patents

US5430854AJul 4, 1995

Simd with selective idling of individual processors based on stored conditional flags, and with consensus among all flags used for conditional branching

INTEL CORP60 citations95

US5548793AAug 20, 1996

System for controlling arbitration using the memory request signal types generated by the plurality of datapaths

INTEL CORP17 citations81

US5530884AJun 25, 1996

System with plurality of datapaths having dual-ported local memory architecture for converting prefetched variable length data to fixed length decoded data

INTEL CORP18 citations81

US5517665AMay 14, 1996

System for controlling arbitration using the memory request signal types generated by the plurality of datapaths having dual-ported local memory architecture for simultaneous data transmission

INTEL CORP11 citations72

SUN MICROSYSTEMS INC

3 patents

US5935249AAug 10, 1999

Mechanism for embedding network based control systems in a local network interface device

SUN MICROSYSTEMS INC264 citations97

US6795923B1Sep 21, 2004

Mechanism for embedding network based control systems in a local network interface device

SUN MICROSYSTEMS INC53 citations95

US6812046B2Nov 2, 2004

Method and apparatus for electronically aligning capacitively coupled chip pads

SUN MICROSYSTEMS INC16 citations84

ERGO COMPUTING INC

1 patent

US5123095AJun 16, 1992

Integrated scalar and vector processors with vector addressing by the scalar processor

ERGO COMPUTING INC128 citations97

A I ARCHITECTS INC

1 patent

US5018062AMay 21, 1991

Method and apparatus for overriding a ROM routine in response to a reset

A I ARCHITECTS INC17 citations70

PAPADOPOULOS GREGORY M

MASSACHUSETTS INST TECHNOLOGY

Data processing system with synchronization coprocessor for multiple threads

Data processing system with synchronization coprocessor for multiple threads

Particle interaction processing system

Tagged token data processing system with operand matching in activation frames

Particle interaction processing system

Efficient data processor instrumentation for systematic program debugging and development

System and method for construction of lists of deferred service requests

INTEL CORP

Simd with selective idling of individual processors based on stored conditional flags, and with consensus among all flags used for conditional branching

System for controlling arbitration using the memory request signal types generated by the plurality of datapaths

System with plurality of datapaths having dual-ported local memory architecture for converting prefetched variable length data to fixed length decoded data

System for controlling arbitration using the memory request signal types generated by the plurality of datapaths having dual-ported local memory architecture for simultaneous data transmission

SUN MICROSYSTEMS INC

Mechanism for embedding network based control systems in a local network interface device

Mechanism for embedding network based control systems in a local network interface device

Method and apparatus for electronically aligning capacitively coupled chip pads

ERGO COMPUTING INC

Integrated scalar and vector processors with vector addressing by the scalar processor

A I ARCHITECTS INC

Method and apparatus for overriding a ROM routine in response to a reset