Inventor

TAI SUNG-SHAN

US44 patents

⚠️ This page may combine multiple inventors who share the name “TAI SUNG-SHAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TAI SUNG-SHAN

ALPHA & OMEGA SEMICONDUCTOR

Dual gate oxide trench MOSFET with channel stop trench

One time programmable memory cell

Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching

Device structure and manufacturing method using HDP deposited source-body implant block

Shallow source MOSFET

Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process

Shallow source MOSFET

Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer

Process of forming ultra thin wafers having an edge support ring

Processes for manufacturing MOSFET devices with excessive round-hole shielded gate trench (SGT)

Completely decoupled high voltage and low voltage transistor manufacturing processes

Excessive round-hole shielded gate trench (SGT) MOSFET devices and manufacturing processes

Shallow source MOSFET

Polysilicon control etch-back indicator

Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions

Polysilicon control etch-back indicator

Device structure and manufacturing method using HDP deposited source-body implant block

Device configuration of asymmetrical DMOSFET with schottky barrier source

One-time programmable (OTP) memory cell

TAI SUNG-SHAN

Dual gate oxide trench MOSFET with channel stop trench

Method for making dual gate oxide trench MOSFET with channel stop using three or four masks process

Semiconductor power device having shielding electrode for improving breakdown voltage

Direct contact in trench with three-mask shield gate process

Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET

Direct contact in trench with three-mask shield gate process

Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET

Method of forming a self-aligned contact opening in MOSFET

Manufacturing method power semiconductor device

HU YONGZHONG

Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier source

Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process

Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions

Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions

BHALLA ANUP

Device structure and manufacturing method using HDP deposited source-body implant block

Device structure and manufacturing method using HDP deposited using deposited source-body implant block

Device structure and manufacturing method using HDP deposited source-body implant block

SILICONIX INC

Method of making trench-gated MOSFET having cesium gate oxide layer

Method of forming vertical planar DMOSFET with self-aligned contact

LEE YEEHENG

Fabrication of trench DMOS device having thick bottom shielding oxide

Fabrication of trench DMOS device having thick bottom shielding oxide

WANG YU

Polysilicon control etch back indicator

Polysilicon control etch-back indicator

PAN JI

Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching

FENG TAO

Process of forming ultra thin wafers having an edge support ring

YEH TENG-HAO

Trench type power transistor device