Inventor

BHALLA ANUP

US301 patents

⚠️ This page may combine multiple inventors who share the name “BHALLA ANUP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BHALLA ANUP

ALPHA & OMEGA SEMICONDUCTOR

Power MOS device

Method for forming nanotube semiconductor devices

Self aligned trench MOSFET with integrated diode

Approach to integrate Schottky in MOSFET

Oxide terminated trench MOSFET with three or four masks

Oxide terminated trench MOSFET with three or four masks

Integration of sense FET into discrete power MOSFET

Power MOS device with conductive contact layer

High density trench mosfet with single mask pre-defined gate and contact trenches

Power MOS device

Integration of a sense FET into a discrete power MOSFET

High density trench MOSFET with single mask pre-defined gate and contact trenches

Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact

Trench junction barrier controlled Schottky device with top and bottom doped regions for enhancing forward current in a vertical direction

Shielded gate trench (SGT) MOSFET devices and manufacturing processes

Power MOS device

Nano-tube MOSFET technology and devices

Planar split-gate high-performance MOSFET structure and manufacturing method

Power semiconductor package

BHALLA ANUP

MOSFET using gate work function engineering for switching applications

Planar SRFET using no additional masks and layout method

Cascode scheme for improved device switching behavior

Power MOS device fabrication

Split-gate structure in trench-based silicon carbide power device

Shielded gate trench (SGT) MOSFET devices and manufacturing processes

High voltage field balance metal oxide field effect transistor (FBM)

Normally off gallium nitride field effect transistors (FET)

MOS device with integrated schottky diode in active region contact trench

YILMAZ HAMZA

Nanotube semiconductor devices

Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact

Stacked dual chip package and method of fabrication

SILICONIX INC

Barrier accumulation-mode MOSFET

Structures of and methods of fabricating trench-gated MIS devices

Vertical structure for semiconductor wafer-level chip scale packages

BOBDE MADHUR

Lateral super junction device with high substrate-drain breakdown and built-in avalanche clamp diode

Buried field ring field effect transistor (BUF-FET) integrated with cells implanted with hole supply path

TVS with low capacitance and forward voltage drop with depleted SCR as steering diode

LUI SIK

Self aligned trench MOSFET with integrated diode

Approach to integrate Schottky in MOSFET

Oxide terminated trench MOSFET with three or four masks

UNITED SILICON CARBIDE INC

Cascode switching circuit

Silicon carbide MOSFET with integrated MOS diode

VISHAY SILICONIX

Structures of and methods of fabricating trench-gated MIS devices

Structures of and methods of fabricating trench-gated MIS devices

GUAN LINGPENG

Termination design for high voltage device

Corner layout for superjunction device

CHEN JOHN

Method of forming a self-aligned charge balanced power DMOS

Shielded gate trench MOSFET device and fabrication

ALPHS & OMEGA SEMICONDUCTOR LT

Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact

LIU KAI

Dual-leadframe multi-chip package and method of manufacture