Inventor

NING SHEYANG

US26 patents

⚠️ This page may combine multiple inventors who share the name “NING SHEYANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NING SHEYANG

MICRON TECHNOLOGY INC

Memory devices with four data line bias levels

In-line programming adjustment of a memory cell in a memory sub-system

Intervallic dynamic start voltage and program verify sampling in a memory sub-system

Fast bit erase for upper tail tightening of threshold voltage distributions

Volatile data storage in NAND memory

In-line programming adjustment of a memory cell in a memory sub-system

Fast bit erase for upper tail tightening of threshold voltage distributions

Reducing maximum programming voltage in memory programming operations

Level shifting in all levels programming of a memory device in a memory sub-system

Apparatus for determining memory cell data states

Memory devices with four data line bias levels

All levels programming of a memory device in a memory sub-system

Apparatus and methods for determining memory cell data states

Intervallic dynamic start voltage and program verify sampling in a memory sub-system

Managing dielectric stress of a memory device using controlled ramping slopes

Managing dielectric stress of a memory device using controlled ramping slopes

Overwrite mode in memory programming operations

Charge loss acceleration during programming of memory cells in a memory sub-system

Establishing bitline, wordline and boost voltages to manage a maximum program voltage level during all levels programming of a memory device

All level coarse/fine programming of memory cells

Concurrent slow-fast memory cell programming

NANTERO INC

Devices and methods for programming resistive change elements

Devices for programming resistive change elements in resistive change element arrays

Methods for error correction with resistive change element arrays

Resistive change element cells sharing selection devices

Methods for error correction with resistive change element arrays