Inventor

FAVOR JOHN GREGORY

US66 patents

⚠️ This page may combine multiple inventors who share the name “FAVOR JOHN GREGORY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FAVOR JOHN GREGORY

ORACLE AMERICA INC

Data cache rollbacks for failed speculative traces with memory operations

Memory ordering queue/versioning cache circuit

Virtual core management

Virtual core management

Abort prioritization in a trace-based processor

Trace optimization via fusing operations of a target architecture operation set

Prediction of data values read from memory by a microprocessor using the storage destination of a load operation

Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit

Trace unit with a trace builder

Trace based rollback of a speculatively updated cache

Prediction of data values read from memory by a microprocessor using a dynamic confidence threshold

Trace unit

Promoting and appending traces in an instruction processing circuit based upon a bias value

Method and system for promoting traces in an instruction processing circuit

Cache rollback acceleration via a bank based versioning cache ciruit

Trace based deallocation of entries in a versioning cache circuit

Checking for a memory ordering violation after a speculative cache write

Rolling back a speculative update of a non-modifiable cache line

Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer

Concurrent vs. low power branch prediction

Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder

Memory ordering queue tightly coupled with a versioning cache circuit

Emit vector optimization of a trace

Flag optimization of a trace

System and method for ensuring coherency in trace execution

ADVANCED MICRO DEVICES INC

Method and apparatus for debugging an integrated circuit

Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions

Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions

Method and apparatus for executing string instructions

Microprocessor modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instructions

Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts

Cache controller with table walk logic tightly coupled to second level access logic

Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts

SUN MICROSYSTEMS INC

Executing functions determined via a collection of operations from translated instructions

Adaptive computing ensemble microprocessor architecture

Reduced-power memory with per-sector ground control

Prefetch hardware efficiency via prefetch hint instructions

Software hint to specify the preferred branch prediction to use for a branch instruction

Reduced-power memory with per-sector power/ground control and early address

Flag management in processors enabled for speculative execution of micro-operation traces

CHENG YU QING

Virtual core management

Virtual core management

Virtual core remapping based on temperature

ASHCRAFT MATTHEW W

Outstanding load miss buffer with shared entries

Load store unit with load miss result buffer

Load miss result buffer with shared data lines

AMPERE COMPUTING LLC

Clock control based on voltage associated with a microprocessor

BEN-MEIR AMOS

Method and apparatus for performing table lookup

ASHCRAFT MATTHEW WILLIAM

Symbolic renaming optimization of a trace

KRUCKEMYER DAVID A

Multi-level store merging in a cache and memory hierarchy