Inventor

SHAH SALIM A

US15 patents

⚠️ This page may combine multiple inventors who share the name “SHAH SALIM A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

10 patents

US5550490AAug 27, 1996

Operation of a multi-slice processor implementing a mechanism to overcome a system hang

IBM0 citations51

US9996359B2Jun 12, 2018

Fast multi-width instruction issue in parallel slice processor

IBM0 citations51

US9983879B2May 29, 2018

Operation of a multi-slice processor implementing dynamic switching of instruction issuance order

IBM1 citations51

US9298420B2Mar 29, 2016

Identification of the bit position of a selected instance of a particular bit value in a binary bit string

IBM0 citations45

US10740107B2Aug 11, 2020

Operation of a multi-slice processor implementing load-hit-store handling

IBM0 citations41

US10445100B2Oct 15, 2019

Broadcasting messages between execution slices for issued instructions indicating when execution results are ready

IBM0 citations41

ADVANCED MICRO DEVICES INC

5 patents

US5206828AApr 27, 1993

Special carry save adder for high speed iterative division

ADVANCED MICRO DEVICES INC25 citations92

US5128891AJul 7, 1992

High speed divider with square root capability

ADVANCED MICRO DEVICES INC45 citations88

US5737564AApr 7, 1998

Cache memory system having multiple caches with each cache mapped to a different area of main memory to avoid memory contention and to lessen the number of cache snoops

ADVANCED MICRO DEVICES INC12 citations72

US5586298ADec 17, 1996

Effective use of memory bus in a multiprocessing environment by controlling end of data intervention by a snooping cache

ADVANCED MICRO DEVICES INC11 citations72

US5502828AMar 26, 1996

Reducing memory access in a multi-cache multiprocessing environment with each cache mapped into different areas of main memory to avoid contention

ADVANCED MICRO DEVICES INC9 citations72

SHAH SALIM A

IBM

Single-rail self-resetting logic circuitry

Fast multi-width instruction issue in parallel slice processor

Merging status and control data in a reservation station

Fast multi-width instruction issue in parallel slice processor

Operation of a multi-slice processor implementing a mechanism to overcome a system hang

Fast multi-width instruction issue in parallel slice processor

Operation of a multi-slice processor implementing dynamic switching of instruction issuance order

Identification of the bit position of a selected instance of a particular bit value in a binary bit string

Operation of a multi-slice processor implementing load-hit-store handling

Broadcasting messages between execution slices for issued instructions indicating when execution results are ready

ADVANCED MICRO DEVICES INC

Special carry save adder for high speed iterative division

High speed divider with square root capability

Cache memory system having multiple caches with each cache mapped to a different area of main memory to avoid memory contention and to lessen the number of cache snoops

Effective use of memory bus in a multiprocessing environment by controlling end of data intervention by a snooping cache

Reducing memory access in a multi-cache multiprocessing environment with each cache mapped into different areas of main memory to avoid contention