Inventor

STRACHAN ANDY

US27 patents

⚠️ This page may combine multiple inventors who share the name “STRACHAN ANDY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STRACHAN ANDY

NAT SEMICONDUCTOR CORP

Power MOSFET cell with a crossed bar shaped body contact area

Memory cell with a capacitive structure as a control gate and method of forming the memory cell

Method of forming a zener diode in a npn and pnp bipolar process flow that requires no additional steps to set the breakdown voltage

Silicide bridged anti-fuse

Vertical photodiode with heavily-doped regions of alternating conductivity types

Compact ballasting region design for snapback N-MOS ESD protection structure using multiple local N+ region blocking

Method and device for improving hot carrier reliability of an LDMOS transistor using drain ring over-drive bias

LDMOS transistor structure for improving hot carrier reliability

Method of forming a silicide bridged anti-fuse with a tungsten plug metalization process

Method of measuring the leakage current of a deep trench isolation structure

Method of forming a semiconductor structure with non-uniform metal widths

Power transistor structure with non-uniform metal widths

High-voltage silicon controlled rectifier structure with improved punch through resistance

Circuit and method of forming the circuit having subsurface conductors

Multi-source, multi-gate MOS transistor with a drain region that is wider than the source regions

Trim zener using double poly process

Method of controlling the breakdown voltage of BSCRs and BJT clamps

Method of forming a high-voltage silicon controlled rectifier structure with improved punch through resistance

Single mask control of doping levels

Semiconductor interconnect and method of providing interconnect using a contact region

System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird&#39;s beak structure in the manufacture of a semiconductor device

Electrical test structure and method for characterization of deep trench sidewall reliability

Method of forming a circuit having subsurface conductors

System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird&#39;s beak structure in the manufacture of a semiconductor device

Wedge-shaped high density capacitor and method of making the capacitor

System and method for increasing breakdown voltage of LOCOS isolated devices

TEXAS INSTRUMENTS INC

Contact array optimization for ESD devices

System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device

System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device