Inventor

ROZAS GUILLERMO J

US55 patents

⚠️ This page may combine multiple inventors who share the name “ROZAS GUILLERMO J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ROZAS GUILLERMO J

TRANSMETA CORP

Translation consistency checking for modified target instructions by comparing to original copy

Switching to original modifiable instruction copy comparison check to validate prior translation when translated sub-area protection exception slows down operation

Method and apparatus for enhancing scheduling in an advanced microprocessor

Methods and systems employing a flag for deferring exception handling to a commit or rollback point

Method and apparatus for scheduling to reduce space and increase speed of microprocessor operations

Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds threshold

Method and system for caching attribute data for matching attributes with physical addresses

Method and system for caching attribute data for matching attributes with physical addresses

Floating point exception handling in pipelined processor using special instruction to detect generated exception and execute instructions singly from known correct state

Memory management methods and systems that support cache consistency

Methods and systems for maintaining information for locating non-native processor instructions when executing native processor instructions

Exception handling with inserted status check command accommodating floating point instruction forward move across branch

Method and apparatus for improving segmented memory addressing

Method and apparatus for improving segmented memory addressing

ROZAS GUILLERMO J

Checking for exception by floating point instruction reordered across branch by comparing current status in FP status register against last status copied in shadow register

Method and system for automatically calibrating intra-cycle timing relationships for sampling signals for an integrated circuit device

Checkpointed buffer for re-entry from runahead

Memory protection and address translation hardware support for virtual machines

Method and system for validating a computer system

Method and apparatus for enhancing scheduling in an advanced microprocessor

Setting a flag bit to defer event handling to a safe point in an instruction stream

Memory management for cache consistency

Coherence de-coupling buffer

Multi-threading based on rollback

Multi-threaded transactional memory coherence

Setting a flag bit to defer event handling to one of multiple safe points in an instruction stream

Method and system for elastic signal pipelining

Method and apparatus for enhancing scheduling in an advanced microprocessor

NVIDIA CORP

Execution pipeline data forwarding

Lazy runahead operation for a microprocessor

Profiling code portions to generate translations

Dynamic reconfiguration of a multi-core processor to a unified core

Lazy runahead operation for a microprocessor

Queued instruction re-dispatch after runahead

ANVIN H PETER

Method and system for caching attribute data for matching attributes with physical addresses

Method and system for caching attribute data for matching attributes with physical addresses

Method and apparatus for improving segmented memory addressing

KLAIBER ALEXANDER C

System and method for handling direct memory accesses

Handling direct memory accesses

System and method for handling direct memory accesses

SCHNAITTER WILLIAM N

Signal generator with output frequency greater than the oscillator frequency

Signal generator with output frequency greater than the oscillator frequency

Signal generator with output frequency greater than the oscillator frequency

INTELLECTUAL VENTURE FUNDING LLC

Method and system for caching attribute data for matching attributes with physical addresses

Method and system for caching attribute data for matching attributes with physical addresses

BANNING JOHN

Checking for instruction invariance to execute previously obtained translation code by comparing instruction to a copy stored when write operation to the memory portion occur

Consistency checking of source instruction to execute previously translated instructions between copy made upon occurrence of write operation to memory and current version

INTELLECTUAL VENTURES HOLDING 81 LLC

Coherence de-coupling buffer

VMWARE INC

Ordinary write in distributed system maintaining data storage integrity

FACEBOOK INC

Coherence de-coupling buffer