Inventor
MONDAL KRISHNENDU
IN22 patents
⚠️ This page may combine multiple inventors who share the name “MONDAL KRISHNENDU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
19 patentsUS6768694B2Jul 27, 2004
Method of electrically blowing fuses under control of an on-chip tester interface apparatus
IBM84 citations96
US6922649B2Jul 26, 2005
Multiple on-chip test runs and repairs for memories
IBM20 citations92
US6928377B2Aug 9, 2005
Self-test architecture to implement data column redundancy in a RAM
IBM33 citations91
US9881694B2Jan 30, 2018
Built-in-self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
IBM6 citations82
US8914688B2Dec 16, 2014
System and method of reducing test time via address aware BIST circuitry
IBM8 citations80
US8853847B2Oct 7, 2014
Stacked chip module with integrated circuit chips having integratable and reconfigurable built-in self-maintenance blocks
IBM5 citations73
US10971243B2Apr 6, 2021
Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
IBM1 citations71
US10692584B2Jun 23, 2020
Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
IBM1 citations71
US10199121B2Feb 5, 2019
Simultaneous scan chain initialization with disparate latches
IBM2 citations71
US10096377B1Oct 9, 2018
Simultaneous scan chain initialization with disparate latches
IBM2 citations71
US10026498B1Jul 17, 2018
Simultaneous scan chain initialization with disparate latches
IBM3 citations71
US8918690B2Dec 23, 2014
Decreasing power supply demand during BIST initializations
IBM3 citations62
US11295829B2Apr 5, 2022
Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
IBM0 citations61
US10553302B2Feb 4, 2020
Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
IBM0 citations51
US9859019B1Jan 2, 2018
Programmable counter to control memory built in self-test
IBM0 citations51
US9715942B2Jul 25, 2017
Built-in self-test (BIST) circuit and associated BIST method for embedded memories
IBM1 citations51
US10658062B2May 19, 2020
Simultaneous scan chain initialization with disparate latches
IBM0 citations50
US10586606B2Mar 10, 2020
Simultaneous scan chain initialization with disparate latches
IBM0 citations50
US9773570B2Sep 26, 2017
Built-in-self-test (BIST) test time reduction
IBM0 citations41