Inventor

YU XIAOJUN

US62 patents

⚠️ This page may combine multiple inventors who share the name “YU XIAOJUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YU XIAOJUN

IBM

Method of providing threshold voltage adjustment through gate dielectric stack modification

Dummy gate interconnect for semiconductor device

Tucked active region without dummy poly for performance boost and variation reduction

MOS having a sic/sige alloy stack

Asymmetric semiconductor devices and method of fabricating

Metal gate compatible flash memory gate stack

Electrical antifuse having a multi-thickness dielectric layer

Semiconductor process temperature optimization

Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor

Post-gate shallow trench isolation structure formation

YU XIAOJUN

Tucked active region without dummy poly for performance boost and variation reduction

Intra die variation monitor using through-silicon via

Wordline voltage transfer apparatus, systems, and methods

Delayed activation of selected wordlines in memory

Erase operation control sequencing apparatus, systems, and methods

Wordline voltage transfer apparatus, systems, and methods

Erase operation control sequencing apparatus, systems, and methods

Post-gate shallow trench isolation structure formation

Selective partial gate stack for improved device isolation

SHENZHEN ROYOLE TECHNOLOGIES CO LTD

Tiled OLED display and manufacturing method thereof

TFT array substrate structure based on OLED

Manufacturing method of a thin film transistor and pixel unit thereof

Substrate and method for fabricating flexible electronic device and rigid substrate

Manufacturing method of a thin film transistor and pixel unit thereof

Self-aligned metal oxide thin-film transistor component and manufacturing method thereof

CYPRESS SEMICONDUCTOR CORP

Systems, methods, and apparatus for memory cells with common source lines

Non-volatile memory and method of operating the same

Systems, methods, and apparatus for memory cells with common source lines

Systems, methods, and apparatus for memory cells with common source lines

MICRON TECHNOLOGY INC

Erase operation control sequencing apparatus, systems, and methods

Wordline voltage transfer apparatus, systems, and methods

Delayed activation of selected wordlines in memory

CHIDAMBARRAO DURESETI

Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same

CMOS having a SiC/SiGe alloy stack

Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same

ROYOLE CORP

Support and detachment of flexible substrates

Substrate-less flexible display and method of manufacturing the same

Manufacturing apparatus for flexible electronics

GLOBALFOUNDRIES INC

Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors

Tucked active region without dummy poly for performance boost and variation reduction

STEVENS INST TECHNOLOGY

Biphasic osteochondral scaffold for reconstruction of articular cartilage

THE TRUSTEES OF THE STEVENS INST OF TECH

Implantable nerve conduit having a polymer fiber spiral guidance channel

STEVENS INSTITUTE OF TECHNOLOGY

Implantable nerve guidance conduits having polymer fiber guidance channel

CHANG PAUL

Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors

GREENE BRIAN J

Threshold voltage adjustment through gate dielectric stack modification

ENJOIN IND LTD

Gas can spout

BOOTH JR ROGER A

Polysilicon resistor and E-fuse for integration with metal gate and high-k dielectric

SHINERICH IND LTD

Patio heater

ADVANCED TECH & MATERIALS CO LTD

Method for preparing rare-earth permanent magnetic material with grain boundary diffusion using composite target by vapor deposition

UNIV NORTHEASTERN

One-way rapid electromagnetic unloading device suitable for true triaxial testing machine