Inventor

LIAW JHON JHY

TW751 patents

⚠️ This page may combine multiple inventors who share the name “LIAW JHON JHY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIAW JHON JHY

TAIWAN SEMICONDUCTOR MFG CO LTD

Fin-based strap cell structure

Method of manufacturing semiconductor device and semiconductor device

Fin-based semiconductor device including a metal gate diffusion break structure with a conformal dielectric layer

Structure and method for an SRAM circuit

Semiconductor device, semiconductor device layout, and method of manufacturing semiconductor device

Semiconductor circuit with metal structure and manufacturing method

Semiconductor device layout

SRAM array

Integrated circuit chip and manufacturing method thereof

Integrated standard cell structure

Structure and method for FinFET device with asymmetric contact

FinFET SRAM having discontinuous PMOS fin lines

Interconnect structure with misaligned metal lines coupled using different interconnect layer

SRAM arrays and methods of manufacturing same

SRAM structure with reduced capacitance and resistance

SRAM cells with vertical gate-all-round MOSFETs

Two-port SRAM connection structure

Memory array with bit-lines connected to different sub-arrays through jumper structures

Dual-port SRAM cell structure with vertical devices

Dual-port static random access memory

Memory array with strap cells

Multi-stage fin formation methods and structures thereof

Integrated circuit chip having two types of memory cells

Layout of static random access memory array

TAIWAN SEMICONDUCTOR MFG

Contact plugs in SRAM cells and the method of forming the same

Structure and method for FinFET SRAM

SRAM cells with vertical gate-all-round MOSFETs

Memory chip and layout design for manufacturing same

Cell layout for SRAM FinFET transistors

Methods and apparatus for FinFET SRAM arrays in integrated circuits

Integrated semiconductor structure for SRAM cells

Method for improving threshold voltage stability of a MOS device

Method of forming a static random access memory with a buried local interconnect

Laterally recessed tungsten silicide gate structure used with a self-aligned contact structure including a straight walled sidewall spacer while filling recess

Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer

Using an extra boron implant to improve the NMOS reverse narrow width effect in shallow trench isolation process

Layout for multiple-Fin SRAM cell

Power grid design for split-word line style memory cell

SRAM cell for soft-error rate reduction and cell stability improvement

Metal gate structure for MOS devices

Method to suppress CMOS device latchup and improve interwell isolation

Method for making a dual gate structure for CMOS device

Fuse window guard ring structure for nitride capped self aligned contact processes

Two step barrier process

LIAW JHON JHY

Cell structure for dual-port SRAM

Gate stack of fin field effect transistor with slanted sidewalls

Layout for multiple-fin SRAM cell

Fully balanced dual-port memory cell

LIAW JHON-JHY

Methods and apparatus for finFET SRAM arrays in integrated circuits

Memory cell