Inventor
STONECYPHER WILLIAM F
US19 patents
Patents
19 patentsUS7142612B2Nov 28, 2006
Method and apparatus for multi-level signaling
RAMBUS INC193 citations99
US6473439B1Oct 29, 2002
Method and apparatus for fail-safe resynchronization with minimum latency
RAMBUS INC140 citations99
US7308058B2Dec 11, 2007
Transparent multi-mode PAM interface
RAMBUS INC105 citations98
US6608507B2Aug 19, 2003
Memory system including a memory device having a controlled output driver characteristic
RAMBUS INC91 citations98
US6462591B2Oct 8, 2002
Semiconductor memory device having a controlled output driver characteristic
RAMBUS INC115 citations98
US6094075AJul 25, 2000
Current control technique
RAMBUS INC114 citations98
US6949958B2Sep 27, 2005
Phase comparator capable of tolerating a non-50% duty-cycle clocks
RAMBUS INC52 citations96
US6870419B1Mar 22, 2005
Memory system including a memory device having a controlled output driver characteristic
RAMBUS INC45 citations96
US6556052B2Apr 29, 2003
Semiconductor controller device having a controlled output driver characteristic
RAMBUS INC68 citations96
US6294934B1Sep 25, 2001
Current control technique
RAMBUS INC47 citations96
US6975160B2Dec 13, 2005
System including an integrated circuit memory device having an adjustable output voltage setting
RAMBUS INC15 citations92
US7162672B2Jan 9, 2007
Multilevel signal interface testing with binary test apparatus by emulation of multilevel signals
RAMBUS INC21 citations91
US9892771B2Feb 13, 2018
Memory controller with dynamic core-transfer latency
RAMBUS INC10 citations84
US7288973B2Oct 30, 2007
Method and apparatus for fail-safe resynchronization with minimum latency
RAMBUS INC11 citations84
US9368172B2Jun 14, 2016
Read strobe gating mechanism
RAMBUS INC9 citations83
US7167039B2Jan 23, 2007
Memory device having an adjustable voltage swing setting
RAMBUS INC6 citations73
US11677391B1Jun 13, 2023
Low-power multi-domain synchronizer
RAMBUS INC0 citations62
US7352234B2Apr 1, 2008
Current control technique
RAMBUS INC1 citations62
US6975159B2Dec 13, 2005
Method of operation in a system having a memory device having an adjustable output voltage setting
RAMBUS INC0 citations51