Inventor
ROZAS GUILLERMO
US30 patents
⚠️ This page may combine multiple inventors who share the name “ROZAS GUILLERMO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ROZAS GUILLERMO
11 patentsUS8239656B2Aug 7, 2012
System and method for identifying TLB entries associated with a physical address of a specified range
ROZAS GUILLERMO56 citations98
US7913058B2Mar 22, 2011
System and method for identifying TLB entries associated with a physical address of a specified range
ROZAS GUILLERMO58 citations98
US8522253B1Aug 27, 2013
Hardware support for virtual machine and operating system context switching in translation lookaside buffers and virtually tagged caches
ROZAS GUILLERMO83 citations97
US7873793B1Jan 18, 2011
Supporting speculative modification in a data cache
ROZAS GUILLERMO24 citations92
US7606979B1Oct 20, 2009
Method and system for conservatively managing store capacity available to a processor issuing stores
ROZAS GUILLERMO17 citations92
US7747896B1Jun 29, 2010
Dual ported replicated data cache
ROZAS GUILLERMO6 citations73
US7971002B1Jun 28, 2011
Maintaining instruction coherency in a translation-based computer system architecture
ROZAS GUILLERMO4 citations63
US7904789B1Mar 8, 2011
Techniques for detecting and correcting errors in a memory device
ROZAS GUILLERMO3 citations63
US7606997B1Oct 20, 2009
Method and system for using one or more address bits and an instruction to increase an instruction set
ROZAS GUILLERMO0 citations51
US8656214B2Feb 18, 2014
Dual ported replicated data cache
ROZAS GUILLERMO0 citations50
US7725656B1May 25, 2010
Braided set associative caching techniques
ROZAS GUILLERMO0 citations38
TRANSMETA CORP
8 patentsUS7380096B1May 27, 2008
System and method for identifying TLB entries associated with a physical address of a specified range
TRANSMETA CORP62 citations98
US7149872B2Dec 12, 2006
System and method for identifying TLB entries associated with a physical address of a specified range
TRANSMETA CORP70 citations98
US6748589B1Jun 8, 2004
Method for increasing the speed of speculative execution
TRANSMETA CORP75 citations98
US7337439B1Feb 26, 2008
Method for increasing the speed of speculative execution
TRANSMETA CORP12 citations93
US7225299B1May 29, 2007
Supporting speculative modification in a data cache
TRANSMETA CORP22 citations92
US7149851B1Dec 12, 2006
Method and system for conservatively managing store capacity available to a processor issuing stores
TRANSMETA CORP19 citations92
US6725361B1Apr 20, 2004
Method and apparatus for emulating a floating point stack in a translation process
TRANSMETA CORP29 citations87
US7478226B1Jan 13, 2009
Processing bypass directory tracking system and method
TRANSMETA CORP9 citations84
NVIDIA CORP
3 patentsUS9582280B2Feb 28, 2017
Branching to alternate code based on runahead determination
NVIDIA CORP4 citations73
US9804854B2Oct 31, 2017
Branching to alternate code based on runahead determination
NVIDIA CORP0 citations52
US9367467B2Jun 14, 2016
System and method for managing cache replacements
NVIDIA CORP0 citations50
KLAIBER ALEXANDER
3 patentsUS7937566B1May 3, 2011
Processing bypass directory tracking system and method
KLAIBER ALEXANDER3 citations61
US9652244B2May 16, 2017
Processing bypass directory tracking system and method
KLAIBER ALEXANDER0 citations50
US8209518B2Jun 26, 2012
Processing bypass directory tracking system and method
KLAIBER ALEXANDER0 citations50