Inventor
OSULLIVAN CONOR
US7 patents
Patents
7 patentsUS9905487B1Feb 27, 2018
Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of V0 via opens
PDF SOLUTIONS INC3 citations84
US9911649B1Mar 6, 2018
Process for making and using mesh-style NCEM pads
PDF SOLUTIONS INC2 citations73
US9911669B1Mar 6, 2018
Integrated circuit including NCEM-enabled, diagonal gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
PDF SOLUTIONS INC0 citations63
US9911670B1Mar 6, 2018
Integrated circuit including NCEM-enabled, via-open/resistance-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gate
PDF SOLUTIONS INC0 citations63
US9911668B1Mar 6, 2018
Integrated circuit including NCEM-enabled, corner gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
PDF SOLUTIONS INC0 citations63
US9905553B1Feb 27, 2018
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells
PDF SOLUTIONS INC0 citations63
US9899276B1Feb 20, 2018
Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
PDF SOLUTIONS INC0 citations63