Inventor

EMMA PHILIP G

US98 patents

⚠️ This page may combine multiple inventors who share the name “EMMA PHILIP G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EMMA PHILIP G

IBM

3-dimensional integrated circuit architecture, structure and method for fabrication thereof

Simultaneous prediction of multiple branches for superscalar processing

Pipeline processing apparatus for executing instructions in three streams, including branch stream pre-execution processor for pre-executing conditional branch instructions

Method and apparatus for reducing latency in set-associative caches using set prediction

Multi-prediction branch prediction mechanism

Methods and apparatus for insulating a branch prediction mechanism from data dependent branch table updates that result from variable test operand locations

Data processing system with fast queue store interposed between store-through caches and a main memory

Posting out-of-sequence fetches

Multiple branch analyzer for prefetching cache lines

Branch prediction mechanism in which a branch history table is updated using an operand sensitive branch table

Chip system architecture for performance enhancement, power reduction and cost reduction

3-dimensional integrated circuit architecture, structure and method for fabrication thereof

Method and apparatus for prefetching branch history information

Processor with low overhead predictive supply voltage gating for leakage power reduction

Backplane assembly with board to board optical interconnections

Optically connectable circuit board with optical component(s) mounted thereon

Methodology for fixing Qcrit at design timing impact

Apparatus for reducing soft errors in dynamic circuits

Method for enabling concurrent misses in a cache memory

Multiple sequence processor system

Method and apparatus for dynamic cache line sectoring in multiprocessor systems

Subroutine return through branch history table

Cache miss facility with stored sequences for data fetching

Cache management for multi-processor systems utilizing bulk cross-invalidate

Processor with demand-driven clock throttling power reduction

Computer processing unit employing a separate millicode branch history table

Case block table for predicting the outcome of blocks of conditional branches having a common operand

Method and apparatus to facilitate direct surface cooling of a chip within a 3D stack of chips using optical interconnect

Method for the asynchronous arbitration of a high frequency bus in a long latency environment

Optically connectable circuit board with optical component(s) mounted thereon

Sectored cache memory

Methods involving memory caches

Electronic substrate with inboard terminal array, perimeter terminal array and exterior terminal array on a second surface and module and system including the substrate

Method and apparatus for dynamically allocating processors

Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches

Digital measuring system and method for integrated circuit chip operating parameters

Error correcting logic system

Error correcting logic system

Integrated circuit chip package with formable intermediate 3D wiring structure

Integrated wafer-level processing system

Heterogeneous core microarchitecture

Storing and comparing three-dimensional objects in three-dimensional storage

High speed data channel including a CMOS VCSEL driver and a high performance photodetector and CMOS photoreceiver

High speed data channel including a CMOS VCSEL driver and a high performance photodetector and CMOS photoreceiver

Method for in-situ continuity check on an optical bus

EMMA PHILIP G

Processor core stacking for efficient collaboration

Branch prediction instructions having mask values involving unloading and loading branch history data

INTRNATIONAL BUSINESS MACHINES

Method and apparatus for the transparent emulation of an existing instruction-set architecture by an arbitrary underlying instruction-set architecture

BOSE PRADIP

Low overhead dynamic thermal management in many-core cluster architecture

KURSUN EREN

Non-volatile memory based reliability and availability mechanisms for a computing device