Inventor

HOOK TERENCE B

US192 patents

⚠️ This page may combine multiple inventors who share the name “HOOK TERENCE B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOOK TERENCE B

IBM

Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices

Extra gate device for nanosheet

CMOS well structure and method of forming the same

Use of deuterated materials in semiconductor processing

Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage

Active pixel sensor cell and method of using

Dual EPI active pixel cell design and method of making the same

Method to perform selective drain engineering with a non-critical mask

Bottom source/drain silicidation for vertical field-effect transistor (FET)

Vertical transistors with merged active area regions

Interlayer via

Structure and method to minimize junction capacitance in nano sheets

Series-connected nanowire structures

Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process

Angled implant process

Silicide block bounded device

Method of forming a complementary active pixel sensor cell

NVRAM utilizing high voltage TFT device and method for making the same

Semiconductor device and method of forming the semiconductor device

Stable work function for narrow-pitch devices

High performance semiconductor memory device with low power consumption

Asymmetrical field effect transistor

Semiconductor manufacturing process for low dislocation defects

Leakage compensation circuit

Hot electron compensation for improved MOS transistor reliability

Interlayer via contacts for monolithic three-dimensional semiconductor integrated circuit devices

Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device

Extra gate device for nanosheet

Integrating a junction field effect transistor into a vertical field effect transistor

Logic gate designs for 3D monolithic direct stacked VTFET

Nanosheet MOSFET with partial release and source/drain epitaxy

Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process

Nanosheet field effect transistors with partial inside spacers

Stable work function for narrow-pitch devices

FinFETs with various fin height

Lateral non-volatile storage cell

Structures and methods for long-channel devices in nanosheet technology

Bipolar transistor compatible with vertical FET fabrication

Extra gate device for nanosheet

Bulk to silicon on insulator device

Devices with multiple threshold voltages formed on a single wafer using strain in the high-K layer

Semiconductor device with different fin pitches

Structure and method to minimize junction capacitance in nano sheets

Estimating transistor characteristics and tolerances for compact modeling

Heat sink for integrated circuit devices

CHENG KANGGUO

Integrated circuit including DRAM and SRAM/logic

FICKE JOEL T

Physically unclonable function implemented through threshold voltage comparison

GLOBALFOUNDRIES INC

Multiple back gate transistor

COOLBAUGH DOUGLAS D

Method of making heat sink for integrated circuit devices

DENNARD ROBERT H

Structure for CMOS ETSOI with multiple threshold voltages and active well bias capability