Inventor
MALLICK ASIT K
US24 patents
⚠️ This page may combine multiple inventors who share the name “MALLICK ASIT K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
18 patentsUS6745346B2Jun 1, 2004
Method for efficiently identifying errant processes in a computer system by the operating system (OS) for error containment and error recovery
INTEL CORP18 citations91
US10048881B2Aug 14, 2018
Restricted address translation to protect against device-TLB vulnerabilities
INTEL CORP10 citations84
US12253958B2Mar 18, 2025
System for address mapping and translation protection
INTEL CORP1 citations74
US11436161B2Sep 6, 2022
System for address mapping and translation protection
INTEL CORP2 citations73
US10503664B2Dec 10, 2019
Virtual machine manager for address mapping and translation protection
INTEL CORP2 citations73
US10263988B2Apr 16, 2019
Protected container key management processors, methods, systems, and instructions
INTEL CORP6 citations73
US9747123B2Aug 29, 2017
Technologies for multi-level virtualization
INTEL CORP6 citations72
US7131029B2Oct 31, 2006
Method for efficiently identifying errant processes in a computer system by the operating system (OS) for error containment and error recovery
INTEL CORP7 citations72
US9239801B2Jan 19, 2016
Systems and methods for preventing unauthorized stack pivoting
INTEL CORP5 citations70
US12020031B2Jun 25, 2024
Methods, apparatus, and instructions for user-level thread suspension
INTEL CORP0 citations62
US11683310B2Jun 20, 2023
Protecting supervisor mode information
INTEL CORP0 citations62
US11023233B2Jun 1, 2021
Methods, apparatus, and instructions for user level thread suspension
INTEL CORP0 citations62
US11019061B2May 25, 2021
Protecting supervisor mode information
INTEL CORP0 citations62
US10999284B2May 4, 2021
Protecting supervisor mode information
INTEL CORP0 citations62
US11354213B2Jun 7, 2022
Utilization metrics for processing engines
INTEL CORP0 citations58
US10324862B2Jun 18, 2019
Supporting oversubscription of guest enclave memory pages
INTEL CORP0 citations52
US10135825B2Nov 20, 2018
Protecting supervisor mode information
INTEL CORP0 citations52
US9069605B2Jun 30, 2015
Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention
INTEL CORP1 citations52