Inventor
YODA HITOSHI
JP4 patents
Patents
4 patentsUS6868472B1Mar 15, 2005
Method of Controlling and addressing a cache memory which acts as a random address memory to increase an access speed to a main memory
FUJITSU LTD47 citations91
US6760810B2Jul 6, 2004
Data processor having instruction cache with low power consumption
FUJITSU LTD10 citations71
US6823406B2Nov 23, 2004
Microprocessor executing a program to guarantee an access order
FUJITSU LTD3 citations61
US7134004B1Nov 7, 2006
Processing device for buffering sequential and target sequences and target address information for multiple branch instructions
FUJITSU LTD7 citations60