Inventor

TAKEUCHI HIDEKI

US108 patents

⚠️ This page may combine multiple inventors who share the name “TAKEUCHI HIDEKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TAKEUCHI HIDEKI

ATOMERA INC

Semiconductor device including resonant tunneling diode structure having a superlattice

Semiconductor device including a superlattice as a gettering layer

Method for making a semiconductor device including a superlattice as a gettering layer

Method for making a semiconductor device including a resonant tunneling diode structure having a superlattice

Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layers

Semiconductor device including a resonant tunneling diode structure with electron mean free path control layers

Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods

Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods

Semiconductor device including a superlattice and replacement metal gate structure and related methods

Vertical semiconductor devices including superlattice punch through stop layer and related methods

Semiconductor devices including superlattice depletion layer stack and related methods

Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance

Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance

Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance

Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods

Method for making a FINFET having reduced contact resistance

Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance

CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice

Method for making CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice

Method for making CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice

Method for making a semiconductor device having reduced contact resistance

Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance

FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance

Method for making CMOS image sensor including pixels with read circuitry having a superlattice

CMOS image sensor including pixels with read circuitry having a superlattice

Method for making CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk

Method for making CMOS image sensor with buried superlattice layer to reduce crosstalk

CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice

CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk

CMOS image sensor with buried superlattice layer to reduce crosstalk

Semiconductor device including a superlattice and an asymmetric channel and related methods

Method for making a semiconductor device including a superlattice and an asymmetric channel and related methods

Method for making a semiconductor device including a superlattice within a recessed etch

Gate-all-around (GAA) device including a superlattice

Semiconductor device including a superlattice and enriched silicon 28 epitaxial layer

Method for making semiconductor device including superlattice with oxygen and carbon monolayers

Semiconductor device including superlattice with oxygen and carbon monolayers

Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer

Methods for making radio frequency (RF) semiconductor devices including a ground plane layer having a superlattice

TOSHIBA KK

Noise suppression circuit, ASIC, navigation apparatus communication circuit, and communication apparatus having the same

Method of reducing circuit data, method of simulating circuit, and medium for storing circuit data reduction program

Semiconductor memory device having redundant circuit

ALOKA CO LTD

Ultrasound diagnosis apparatus

Ultrasound diagnosis apparatus

TOKYO ELECTRON LTD

Plasma processing method and apparatus for eliminating damages in a plasma process of a substrate

Plasma processing method and apparatus for eliminating damages in a plasma process of a substrate

MEARS TECHNOLOGIES INC

Vertical semiconductor devices including superlattice punch through stop layer and related methods

UNIV CALIFORNIA

Damascene process for use in fabricating semiconductor structures having micro/nano gaps

NEC CORP

Method and apparatus for executing transaction programs in parallel

NGK INSULATORS LTD

Column and column device for low pressure-high speed liquid chromatography and a method for using said column device