Inventor

BENTLEY STEVEN

US63 patents

⚠️ This page may combine multiple inventors who share the name “BENTLEY STEVEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BENTLEY STEVEN

GLOBALFOUNDRIES INC

Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure

Methods of forming a nano-sheet transistor device with a thicker gate stack and the resulting device

Devices and methods of forming VFET with self-aligned replacement metal gates aligned to top spacer post top source drain EPI

Insulated epitaxial structures in nanosheet complementary field effect transistors

Methods of forming fins for a FinFET semiconductor device using a mandrel oxidation process

Vertical field effect transistor formation with critical dimension control

Method and structure to control channel length in vertical FET device

Metal layer routing level for vertical FET SRAM and logic cell scaling

Method of forming semiconductor structure including suspended semiconductor layer and resulting structure

Methods of forming transistor devices with different threshold voltages and the resulting products

Method to form defect free replacement fins by H2 anneal

Method, apparatus and system for improved nanowire/nanosheet spacers

Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor

Method of forming vertical field effect transistors with self-aligned gates and gate extensions and the resulting structure

Vertical FET with self-aligned source/drain regions and gate length based on channel epitaxial growth process

Metal layer routing level for vertical FET SRAM and logic cell scaling

Methods of forming gate electrodes on a vertical transistor device

Method of enhancing surface doping concentration of source/drain regions

Negative capacitance matching in gate electrode structures

Integrated circuit structure with stepped epitaxial region

Methods for the production of integrated circuits comprising epitaxially grown replacement structures

Vertical field effect transistor with self-aligned contacts

Method of forming vertical FinFET device having self-aligned contacts

Methods, apparatus, and system for improved nanowire/nanosheet spacers

Methods of forming transistor structures including forming channel material after formation processes to prevent damage to the channel material

Methods of forming embedded source/drain regions on finFET devices

Methods of forming semiconductor devices including an electrically-decoupled fin

Methods of forming merged source/drain regions on integrated circuit products

Methods of forming substrates comprised of different semiconductor materials and the resulting device

Early PTS with buffer for channel doping control

FinFET device including a uniform silicon alloy fin

Device isolation in FinFET CMOS

Method for forming replacement gate structures for vertical transistors

Negative capacitance matching in gate electrode structures

Negative capacitance integration through a gate contact

Vertical nanowires formed on upper fin surface

IBM

Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism

Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism

Vertical channel field-effect transistor (FET) process compatible long channel transistors

Uniform bottom spacer for VFET devices

Self-aligned contact for vertical field effect transistor

Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism

Self-aligned contact for vertical field effect transistor

Uniform bottom spacer for VFET devices

Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism

Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism

GLOBALFOUNDRIES US INC

III-V compound semiconductor layer stacks with electrical isolation provided by a trap-rich layer

Symmetric arrangement of field plates in semiconductor devices

Symmetric arrangement of field plates in semiconductor devices

Substrate with a buried conductor under an active region for enhanced thermal conductivity and RF shielding