Inventor

LOUBET NICOLAS

US223 patents

⚠️ This page may combine multiple inventors who share the name “LOUBET NICOLAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LOUBET NICOLAS

ST MICROELECTRONICS INC

Method of forming a fully substrate-isolated FinFET transistor

Method for the formation of fin structures for FinFET devices

Method to induce strain in 3-D microfabricated structures

FinFET device with isolated channel

Method to induce strain in finFET channels from an adjacent region

Semiconductor device with fin and related methods

Method to induce strain in 3-D microfabricated structures

Semiconductor device with fin and related methods

Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods

Method to induce strain in finFET channels from an adjacent region

Semiconductor device with fin and related methods

Method to co-integrate SiGe and Si channels for finFET devices

Co-integration of tensile silicon and compressive silicon germanium

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region

Method of using a sacrificial gate structure to make a metal gate FinFET transistor

Fully substrate-isolated FinFET transistor

Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer

Semiconductor device with fin and related methods

Method to induce strain in finFET channels from an adjacent region

Method to induce strain in 3-D microfabricated structures

Bulk finFET semiconductor-on-nothing integration

Method to induce strain in finFET channels from an adjacent region

Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer

IBM

Nanosheet FET with box isolation on substrate

Forming nanosheet transistor using sacrificial spacer and inner spacers

Replacement metal gate and inner spacer formation in three dimensional structures using sacrificial silicon germanium

Nanosheet bottom isolation and source or drain epitaxial growth

Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection

Interlayer via contacts for monolithic three-dimensional semiconductor integrated circuit devices

Negative-capacitance steep-switch field effect transistor with integrated bi-stable resistive system

Replacement contact formation for gate contact over active region with selective metal growth

Nanosheet transistor with optimized junction and cladding defectivity control

Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism

Steep-switch field effect transistor with integrated bi-stable resistive system

Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs

Dual shallow trench isolation liner for preventing electrical shorts

GLOBALFOUNDRIES INC

Nanosheet field-effect transistors including a two-dimensional semiconducting material

Wrap-around contacts formed with multiple silicide layers

Nanosheet devices with CMOS epitaxy and method of forming

Methods of forming alternative channel materials on a non-planar semiconductor device and the resulting device

Fin transformation process and isolation structures facilitating different Fin isolation schemes

Methods of forming isolated channel regions for a FinFET semiconductor device and the resulting device

Process for faciltiating fin isolation schemes

LIU QING

Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods

Semiconductor device with an inclined source/drain and associated methods

Electronic device including shallow trench isolation (STI) regions with bottom nitride liner and upper oxide liner and related methods

BASKER VEERARAGHAVAN S

Cut-very-last dual-epi flow

Cut-very-last dual-EPI flow

COMMISSARIAT ENERGIE ATOMIQUE

Method for making superimposed transistors

DORIS BRUCE B

Dual shallow trench isolation liner for preventing electrical shorts