Inventor
MONTANINI PIETRO
US58 patents
⚠️ This page may combine multiple inventors who share the name “MONTANINI PIETRO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
20 patentsUS10388760B1Aug 20, 2019
Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism
IBM4 citations84
US11387319B2Jul 12, 2022
Nanosheet transistor device with bottom isolation
IBM2 citations73
US11183583B2Nov 23, 2021
Vertical transport FET with bottom source and drain extensions
IBM2 citations73
US10916627B2Feb 9, 2021
Nanosheet transistor with fully isolated source and drain regions and spacer pinch off
IBM2 citations73
US10741675B2Aug 11, 2020
Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism
IBM1 citations73
US10636694B2Apr 28, 2020
Dielectric isolation in gate-all-around devices
IBM3 citations73
US10453736B2Oct 22, 2019
Dielectric isolation in gate-all-around devices
IBM3 citations73
US10699965B1Jun 30, 2020
Removal of epitaxy defects in transistors
IBM4 citations72
US12563796B2Feb 24, 2026
Extended lower source/drain for stacked field-effect transistor
IBM0 citations63
US11777034B2Oct 3, 2023
Hybrid complementary field effect transistor device
IBM0 citations63
US11575022B2Feb 7, 2023
Vertical field-effect transistor late gate recess process with improved inter-layer dielectric protection
IBM0 citations63
US11201089B2Dec 14, 2021
Robust low-k bottom spacer for VFET
IBM1 citations63
US10937890B2Mar 2, 2021
Vertical field-effect transistor late gate recess process with improved inter-layer dielectric protection
IBM0 citations63
US12432960B2Sep 30, 2025
Wraparound contact with reduced distance to channel
IBM0 citations62
US12176404B2Dec 24, 2024
Wrap-around contact for nanosheet device
IBM0 citations52
US10790393B2Sep 29, 2020
Utilizing multilayer gate spacer to reduce erosion of semiconductor Fin during spacer patterning
IBM0 citations52
US10756203B2Aug 25, 2020
Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism
IBM0 citations52
US10553705B2Feb 4, 2020
Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism
IBM0 citations52
US10546945B2Jan 28, 2020
Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism
IBM0 citations52
US10243079B2Mar 26, 2019
Utilizing multilayer gate spacer to reduce erosion of semiconductor fin during spacer patterning
IBM0 citations52
ST MICROELECTRONICS SRL
15 patentsUSRE41889EOct 26, 2010
Process for manufacturing high-sensitivity accelerometric and gyroscopic integrated sensors, and sensor thus produced
ST MICROELECTRONICS SRL16 citations93
US6184052B1Feb 6, 2001
Process for manufacturing high-sensitivity capacitive and resonant integrated sensors, particularly accelerometers and gyroscopes, and sensors made therefrom
ST MICROELECTRONICS SRL16 citations93
US6090638AJul 18, 2000
Process for manufacturing high-sensitivity capacitive and resonant integrated sensors, particularly accelerometers and gyroscopes, and sensors made therefrom
ST MICROELECTRONICS SRL20 citations93
US6331444B1Dec 18, 2001
Method for manufacturing integrated devices including electromechanical microstructures, without residual stress
ST MICROELECTRONICS SRL22 citations92
US7629645B2Dec 8, 2009
Folded-gate MOS transistor
ST MICROELECTRONICS SRL24 citations90
US6209394B1Apr 3, 2001
Integrated angular speed sensor device and production method thereof
ST MICROELECTRONICS SRL18 citations90
US6387725B1May 14, 2002
Production method for integrated angular speed sensor device
ST MICROELECTRONICS SRL15 citations84
US6109106AAug 29, 2000
Process for manufacturing high-sensitivity accelerometric and gyroscopic integrated sensors, and sensor thus produced
ST MICROELECTRONICS SRL11 citations74
US6197655B1Mar 6, 2001
Method for manufacturing integrated structures including removing a sacrificial region
ST MICROELECTRONICS SRL11 citations71
US6559035B2May 6, 2003
Method for manufacturing an SOI wafer
ST MICROELECTRONICS SRL5 citations63
US7572703B2Aug 11, 2009
Method for manufacturing a vertical-gate MOS transistor with countersunk trench-gate
ST MICROELECTRONICS SRL2 citations61
US6395618B2May 28, 2002
Method for manufacturing integrated structures including removing a sacrificial region
ST MICROELECTRONICS SRL5 citations60
US7635896B2Dec 22, 2009
SOI device with contact trenches formed during epitaxial growing
ST MICROELECTRONICS SRL5 citations58
USRE41856EOct 26, 2010
Process for manufacturing high-sensitivity accelerometric and gyroscopic integrated sensors, and sensor thus produced
ST MICROELECTRONICS SRL0 citations52
US7999349B2Aug 16, 2011
Front-rear contacts of electronics devices with induced defects to increase conductivity thereof
ST MICROELECTRONICS SRL0 citations51
GLOBALFOUNDRIES INC
6 patentsUS9984936B1May 29, 2018
Methods of forming an isolated nano-sheet transistor device and the resulting device
GLOBALFOUNDRIES INC91 citations97
US10109533B1Oct 23, 2018
Nanosheet devices with CMOS epitaxy and method of forming
GLOBALFOUNDRIES INC23 citations94
US10366931B2Jul 30, 2019
Nanosheet devices with CMOS epitaxy and method of forming
GLOBALFOUNDRIES INC6 citations84
US9806078B1Oct 31, 2017
FinFET spacer formation on gate sidewalls, between the channel and source/drain regions
GLOBALFOUNDRIES INC9 citations84
US10431663B2Oct 1, 2019
Method of forming integrated circuit with gate-all-around field effect transistor and the resulting structure
GLOBALFOUNDRIES INC4 citations73
US9685384B1Jun 20, 2017
Devices and methods of forming epi for aggressive gate pitch
GLOBALFOUNDRIES INC0 citations52
ST MICROELECTRONICS INC
5 patentsUS10103245B2Oct 16, 2018
Embedded shape sige for strained channel transistors
ST MICROELECTRONICS INC6 citations84
US8987827B2Mar 24, 2015
Prevention of faceting in epitaxial source drain transistors
ST MICROELECTRONICS INC6 citations72
US9000564B2Apr 7, 2015
Precision polysilicon resistors
ST MICROELECTRONICS INC6 citations67
US9245955B2Jan 26, 2016
Embedded shape SiGe for strained channel transistors
ST MICROELECTRONICS INC2 citations63
US9755051B2Sep 5, 2017
Embedded shape sige for strained channel transistors
ST MICROELECTRONICS INC0 citations52
SGS THOMSON MICROELECTRONICS
1 patentPIRELLI & C SPA
1 patentINT BUSINESS MACHINES CORPORATION
1 patentMONTANINI PIETRO
1 patentShowing the top 50 of 58 patents by PatentIndex Score.