Inventor
TOPP JAROSLAW
DE15 patents
⚠️ This page may combine multiple inventors who share the name “TOPP JAROSLAW”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
7 patentsUS9311239B2Apr 12, 2016
Power efficient level one data cache access with pre-validated tags
INTEL CORP11 citations78
US9582432B2Feb 28, 2017
Instruction and logic for support of code modification in translation lookaside buffers
INTEL CORP2 citations72
US9973417B2May 15, 2018
Method and apparatus for managing application state in a network interface controller in a high performance computing system
INTEL CORP3 citations71
US10409763B2Sep 10, 2019
Apparatus and method for efficiently implementing a processor pipeline
INTEL CORP6 citations70
US9558121B2Jan 31, 2017
Two-level cache locking mechanism
INTEL CORP2 citations69
US9009413B2Apr 14, 2015
Method and apparatus to implement lazy flush in a virtually tagged cache memory
INTEL CORP2 citations60
US9367477B2Jun 14, 2016
Instruction and logic for support of code modification in translation lookaside buffers
INTEL CORP1 citations51
BOSCH GMBH ROBERT
5 patentsUS11698672B2Jul 11, 2023
Selective deactivation of processing units for artificial neural networks
BOSCH GMBH ROBERT1 citations58
US11593232B2Feb 28, 2023
Method and device for verifying a neuron function in a neural network
BOSCH GMBH ROBERT0 citations58
US10157062B2Dec 18, 2018
Method for operating a microprocessor
BOSCH GMBH ROBERT0 citations51
US11715019B2Aug 1, 2023
Method and device for operating a neural network in a memory-efficient manner
BOSCH GMBH ROBERT0 citations48
US10384689B2Aug 20, 2019
Method for operating a control unit
BOSCH GMBH ROBERT0 citations38