Inventor

KOLTSIDAS IOANNIS

CH78 patents

⚠️ This page may combine multiple inventors who share the name “KOLTSIDAS IOANNIS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KOLTSIDAS IOANNIS

IBM

Cooperative data deduplication in a solid state storage array

Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory

Metadata hardening and parity accumulation for log-structured arrays

Endurance enhancement scheme using memory re-evaluation

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

Wear leveling of a memory array

Non-volatile memory controller cache architecture with support for separation of data streams

Non-volatile memory data storage with low read amplification

Reducing write amplification in solid-state drives by separating allocation of relocate writes from user writes

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

Extending useful life of a non-volatile memory by health grading

Page retirement in a NAND flash memory system

Promotion of partial data segments in flash cache

Techniques for improving deduplication efficiency in a storage system with multiple storage nodes

Reading files stored on a storage system

Storage device with 2D configuration of phase change memory integrated circuits

Network system and method for transferring cryptocurrencies between a user account and a receiving account

Page retirement in a NAND flash memory system

Non-volatile memory controller cache architecture with support for separation of data streams

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

Wear leveling of a memory array

Non-volatile memory system having an increased effective number of supported heat levels

Cache management in a computerized system

Page retirement in a NAND flash memory system

Method and device for managing a memory

Two-level hierarchical log structured array architecture with minimized write amplification

Two-level hierarchical log structured array architecture using coordinated garbage collection for flash arrays

Managing cache memories

Decentralized RAID scheme having distributed parity computation and recovery

Techniques for improving deduplication efficiency in a storage system with multiple storage nodes

Selective space reclamation of data storage memory employing heat and relocation metrics

Storage device with 2D configuration of phase change memory integrated circuits

Log-structured array (LSA) partial parity eviction and reassembly

Non-volatile memory controller cache architecture with support for separation of data streams

Cache allocation in a computerized system

Endurance enhancement scheme using memory re-evaluation

Reducing write amplification in solid-state drives by separating allocation of relocate writes from user writes

Cache allocation in a computerized system

Techniques for supporting in-place updates with a log-structured array controller

BENHASE MICHAEL T

Selective space reclamation of data storage memory employing heat and relocation metrics

Dynamically adjusted threshold for population of secondary cache

Management of partial data segments in dual cache systems

Promotion of partial data segments in flash cache

Adaptive cache promotions in a two level caching system

Dynamically adjusted threshold for population of secondary cache

ELEFTHERIOU EVANGELOS S

Optimizing locations of data accessed by client applications interacting with a storage system

Optimizing locations of data accessed by client applications interacting with a storage system

ASH KEVIN J

Selective population of secondary cache employing heat metrics

KOLTSIDAS IOANNIS

Write cache structure in a storage system