Inventor
NALLURI HEMA CHAND
IN16 patents
⚠️ This page may combine multiple inventors who share the name “NALLURI HEMA CHAND”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
12 patentsUS11748283B1Sep 5, 2023
Scalable I/O virtualization interrupt and scheduling
INTEL CORP3 citations72
US10078879B2Sep 18, 2018
Process synchronization between engines using data in a memory location
INTEL CORP2 citations72
US11288191B1Mar 29, 2022
Range based flushing mechanism
INTEL CORP0 citations62
US12572392B2Mar 10, 2026
Flexible partitioning of GPU resources
INTEL CORP0 citations61
US12499503B2Dec 16, 2025
Multi-render partitioning
INTEL CORP0 citations61
US12197358B2Jan 14, 2025
Scalable I/O virtualization interrupt and scheduling
INTEL CORP0 citations61
US11321262B2May 3, 2022
Interconnected systems fence mechanism
INTEL CORP0 citations52
US11232531B2Jan 25, 2022
Method and apparatus for efficient loop processing in a graphics hardware front end
INTEL CORP0 citations52
US10026142B2Jul 17, 2018
Supporting multi-level nesting of command buffers in graphics command streams at computing devices
INTEL CORP1 citations51
US12436705B2Oct 7, 2025
Dynamically scalable and partitioned copy engine
INTEL CORP0 citations50
US11281837B2Mar 22, 2022
Router-based transaction routing for toggle reduction
INTEL CORP0 citations47
US9489707B2Nov 8, 2016
Sampler load balancing
INTEL CORP1 citations47
NALLURI HEMA CHAND
4 patentsUS9563466B2Feb 7, 2017
Method and apparatus for supporting programmable software context state execution during hardware context restore flow
NALLURI HEMA CHAND0 citations49
US9064437B2Jun 23, 2015
Memory based semaphores
NALLURI HEMA CHAND1 citations49
US10613972B2Apr 7, 2020
Dynamic configuration of caches in a multi-context supported graphics processor
NALLURI HEMA CHAND0 citations39
US9659342B2May 23, 2017
Mid command buffer preemption for graphics workloads
NALLURI HEMA CHAND0 citations39