Inventor

SHEPEREK MICHAEL

US100 patents

⚠️ This page may combine multiple inventors who share the name “SHEPEREK MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHEPEREK MICHAEL

MICRON TECHNOLOGY INC

Bin placement according to program-erase cycles

Memory system with dynamic calibration using a trim management mechanism

Smart sampling for block family scan

Reliability scan assisted voltage bin selection

Block family combination and voltage bin selection

Memory system with dynamic calibration using a variable adjustment mechanism

Voltage offset bin selection by die group for memory devices

Performing threshold voltage offset bin selection by package for memory devices

Memory system with dynamic calibration using a trim management mechanism

Dynamic programing of valley margins of a memory cell

Memory system with dynamic calibration using a variable adjustment mechanism

First-pass dynamic program targeting (DPT)

Providing data of a memory system based on an adjustable error rate

Block family-based error avoidance for memory devices

Open block family duration limited by time and temperature

Adjustment of program verify targets corresponding to a last programming distribution and a programming distribution adjacent to an initial programming distribution

Open block family duration limited by temperature variation

Error avoidance based on voltage distribution parameters of block families

Closing block family based on soft and hard closure criteria

Generating embedded data in memory cells in a memory sub-system

Voltage bin boundary calibration at memory device power up

Dynamic program erase targeting with bit error rate

Write data for bin resynchronization after power loss

Block family-based error avoidance for memory devices

Read level calibration in memory devices using embedded servo cells

Logic based read sample offset in a memory sub system

Estimation of read level thresholds using a data structure

Dynamic background scan optimization in a memory sub-system

Adjustment of program verify targets corresponding to a last programming distribution and a programming distribution adjacent to an initial programming distribution

Open block family duration limited by temperature variation

Block family-based error avoidance for memory devices

Open block family duration limited by time and temperature

Adjustment of a starting voltage corresponding to a program operation in a memory sub-system

Logic based read sample offset in a memory sub-system

Combination scan management for block families of a memory device

Error avoidance based on voltage distribution parameters of block families

First-pass continuous read level calibration

Combining sets of memory blocks in a memory device

Voltage offset bin selection by die group for memory devices

Generating embedded data in memory cells in a memory sub-system

Estimation of read level thresholds using a data structure

Voltage based combining of block families for memory devices

Block family combination and voltage bin selection

Dynamic program erase targeting with bit error rate

Reliability scan assisted voltage bin selection

Read sample offset bit determination in a memory sub-system

Time-based combining for block families of a memory device

Performing threshold voltage offset bin selection by package for memory devices

Smart sampling for block family scan

TEXAS INSTRUMENTS INC

Fly height control for a read/write head in a hard disk drive