Inventor
JAESCHKE CHRISTOPH
DE6 patents
Patents
6 patentsUS7996738B2Aug 9, 2011
Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip
IBM7 citations83
US7886244B2Feb 8, 2011
Driving values to DC adjusted/untimed nets to identify timing problems
IBM4 citations60
US7565636B2Jul 21, 2009
System for performing verification of logic circuits
IBM4 citations60
US7490305B2Feb 10, 2009
Method for driving values to DC adjusted/untimed nets to identify timing problems
IBM2 citations60
US7398494B2Jul 8, 2008
Method for performing verification of logic circuits
IBM3 citations60
US7213220B2May 1, 2007
Method for verification of gate level netlists using colored bits
IBM6 citations60