Inventor
HATTI SUNIL SURESH
IN15 patents
⚠️ This page may combine multiple inventors who share the name “HATTI SUNIL SURESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
13 patentsUS7752499B2Jul 6, 2010
System and method for using resource pools and instruction pools for processor design verification and validation
IBM25 citations91
US7647539B2Jan 12, 2010
System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation
IBM29 citations91
US7669083B2Feb 23, 2010
System and method for re-shuffling test case instruction orders for processor design verification and validation
IBM22 citations89
US7797650B2Sep 14, 2010
System and method for testing SLB and TLB cells during processor design verification and validation
IBM14 citations82
US7747908B2Jun 29, 2010
System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation
IBM14 citations82
US7661023B2Feb 9, 2010
System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation
IBM9 citations82
US7992059B2Aug 2, 2011
System and method for testing a large memory area during processor design verification and validation
IBM15 citations81
US7739570B2Jun 15, 2010
System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation
IBM7 citations72
US7584394B2Sep 1, 2009
System and method for pseudo-random test pattern memory allocation for processor design verification and validation
IBM7 citations72
US7689886B2Mar 30, 2010
System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation
IBM7 citations71
US7966521B2Jun 21, 2011
Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnostics
IBM5 citations62
US8006221B2Aug 23, 2011
System and method for testing multiple processor modes for processor design verification and validation
IBM2 citations58
US8019566B2Sep 13, 2011
System and method for efficiently testing cache congruence classes during processor design verification and validation
IBM1 citations51